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Fri, 31 Oct 2025 05:16:12 -0700 Date: Fri, 31 Oct 2025 14:16:11 +0200 From: Zhi Wang To: Bjorn Helgaas CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 3/5] rust: pci: add a helper to query configuration space size Message-ID: <20251031141611.669c5380.zhiw@nvidia.com> In-Reply-To: <20251030165115.GA1636169@bhelgaas> References: <20251030154842.450518-4-zhiw@nvidia.com> <20251030165115.GA1636169@bhelgaas> Organization: NVIDIA X-Mailer: Claws Mail 4.3.1 (GTK 3.24.33; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F5:EE_|CY8PR12MB7362:EE_ X-MS-Office365-Filtering-Correlation-Id: bd7fa809-bb84-4df3-c1ef-08de1877532f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 12:16:30.8733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd7fa809-bb84-4df3-c1ef-08de1877532f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7362 On Thu, 30 Oct 2025 11:51:15 -0500 Bjorn Helgaas wrote: > On Thu, Oct 30, 2025 at 03:48:40PM +0000, Zhi Wang wrote: > > Expose a safe Rust wrapper for the `cfg_size` field of `struct > > pci_dev`, allowing drivers to query the size of a device's > > configuration space. > > > > This is useful for code that needs to know whether the device > > supports extended configuration space (e.g. 256 vs 4096 bytes) when > > accessing PCI configuration registers and apply runtime checks. > > What is the value of knowing the config space size, as opposed to just > having config space accessors return PCIBIOS_BAD_REGISTER_NUMBER or > similar when trying to read past the implemented size? > Per my understading, the Io trait aims to provide a generic I/O validation that can be reused across different transports - MMIO, PCI, SPI, and others - with each backend implementing its own region boundaries while sharing the same pre-access validation logic. By design, the framework needs to know the valid address range before performing the actual access. Without exposing cfg_size(), we would have to add PCI configuration-specific handling inside the framework. > Apart from pci-sysfs and vfio, I don't really see any drivers that use > pdev->cfg_size today. It is for the framework so far. If we believe that driver doesn't need this in the near term, I can make it private in the next re-spin. Z.