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Fri, 31 Oct 2025 05:48:37 -0700 Date: Fri, 31 Oct 2025 14:48:36 +0200 From: Zhi Wang To: Alice Ryhl CC: , , , , , , , , , , , , , , , , , , , , , , , , , Bjorn Helgaas Subject: Re: [PATCH v3 1/5] rust: io: factor common I/O helpers into Io trait Message-ID: <20251031144836.110ac310.zhiw@nvidia.com> In-Reply-To: References: <20251030154842.450518-1-zhiw@nvidia.com> <20251030154842.450518-2-zhiw@nvidia.com> Organization: NVIDIA X-Mailer: Claws Mail 4.3.1 (GTK 3.24.33; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003440:EE_|MN0PR12MB5716:EE_ X-MS-Office365-Filtering-Correlation-Id: d5dc40b8-ed8b-486c-c9dd-08de187bd7b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 12:48:51.0862 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5dc40b8-ed8b-486c-c9dd-08de187bd7b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003440.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5716 On Fri, 31 Oct 2025 09:07:04 +0000 Alice Ryhl wrote: > On Thu, Oct 30, 2025 at 03:48:38PM +0000, Zhi Wang wrote: > > The previous Io type combined both the generic I/O access > > helpers and MMIO implementation details in a single struct. > >=20 > > To establish a cleaner layering between the I/O interface and its > > concrete backends, paving the way for supporting additional I/O > > mechanisms in the future, Io need to be factored. > >=20 > > Factor the common helpers into a new Io trait, and move the > > MMIO-specific logic into a dedicated Mmio type implementing > > that trait. Rename the IoRaw to MmioRaw and update the bus MMIO > > implementations to use MmioRaw. > >=20 > > No functional change intended. > >=20 > > Cc: Alexandre Courbot > > Cc: Bjorn Helgaas > > Cc: Danilo Krummrich > > Cc: John Hubbard > > Signed-off-by: Zhi Wang >=20 > > +/// Represents a region of I/O space of a fixed size. > > +/// > > +/// Provides common helpers for offset validation and address > > +/// calculation on top of a base address and maximum size. > > +/// > > +/// Types implementing this trait (e.g. MMIO BARs or PCI config > > +/// regions) can share the same accessors. > > +pub trait Io { >=20 > I would consider moving SIZE to an associated constant. >=20 > pub trait Io { > const MIN_SIZE: usize; > =09 > ... > } >=20 > If it's a generic parameter, then the same type can implement both > Io<5> and Io<7> at the same time, but I don't think it makes sense > for a single type to implement Io with different minimum sizes. >=20 I see your point. It also makes the code look cleaner. =46rom my understanding, this is essentially a choice between performing static boundary checks through the type system using const generics, or using build_assert!() with a trait or struct-associated constant. Let me take a closer look and experiment a bit with it. :) > > /// Returns the base address of this mapping. > > - #[inline] ...ditto > > + /// Infallible 64-bit write with compile-time bounds check > > (64-bit only). > > + #[cfg(CONFIG_64BIT)] > > + fn write64(&self, _value: u64, _offset: usize) { > > + () > > + } > > + > > + /// Fallible 8-bit write with runtime bounds check. > > + fn try_write8(&self, value: u8, offset: usize) -> Result; > > + > > + /// Fallible 16-bit write with runtime bounds check. > > + fn try_write16(&self, value: u16, offset: usize) -> Result; > > + > > + /// Fallible 32-bit write with runtime bounds check. > > + fn try_write32(&self, value: u32, offset: usize) -> Result; > > + > > + /// Fallible 64-bit write with runtime bounds check (64-bit > > only). > > + #[cfg(CONFIG_64BIT)] > > + fn try_write64(&self, _value: u64, _offset: usize) -> Result { > > + Err(ENOTSUPP) > > + } >=20 > Why are there default implementations for all of these trait methods? > I would suggest not providing any default implementations at all. >=20 Yeah, I actually tried that in an earlier version. I noticed that each backend is a bit different =E2=80=94 for example, the P= CI config space routines don=E2=80=99t have read64()/write64() either. By design, we don=E2=80=99t provide infallible versions for the PCI config spa= ce backend (unlike the MMIO one). Other backends might have similar cases as well. So I ended up keeping the trait=E2=80=99s default implementation "minimal",= only including the methods every backend really has to implement. The default impls are mainly there to catch situations where a driver calls something it shouldn=E2=80=99t. I should probably make the compiler complain when an infallible op isn=E2= =80=99t supported by a given backend. And if you have any ideas on making this more elegant, I=E2=80=99m all ears. :) Z. > Alice