Re: [RESEND v13 10/25] cxl/pci: Update RAS handler interfaces to also support CXL Ports

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Tue, 4 Nov 2025 11:02:50 -0600
Terry Bowman <terry.bowman@amd.com> wrote:

> CXL PCIe Port Protocol Error handling support will be added to the
> CXL drivers in the future. In preparation, rename the existing
> interfaces to support handling all CXL PCIe Port Protocol Errors.
> 
> The driver's RAS support functions currently rely on a 'struct
> cxl_dev_state' type parameter, which is not available for CXL Port
> devices. However, since the same CXL RAS capability structure is
> needed across most CXL components and devices, a common handling
> approach should be adopted.
> 
> To accommodate this, update the __cxl_handle_cor_ras() and
> __cxl_handle_ras() functions to use a `struct device` instead of
> `struct cxl_dev_state`.
> 
> No functional changes are introduced.
> 
> [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> 
One additional comment inline.

> ---
> 
> Changes in v12->v13:
> - Added Ben's review-by
> ---
>  drivers/cxl/core/core.h    | 15 ++++++---------
>  drivers/cxl/core/ras.c     | 12 ++++++------
>  drivers/cxl/core/ras_rch.c |  4 ++--
>  3 files changed, 14 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index c30ab7c25a92..1a419b35fa59 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -7,6 +7,7 @@
>  #include <linux/pci.h>
>  #include <cxl/mailbox.h>
>  #include <linux/rwsem.h>
> +#include <linux/pci.h>

Similar to earlier. Not setting what is no here that is pci specific
that wasn't before.  Maybe a forwards def of
struct device is needed? 

>  
>  extern const struct device_type cxl_nvdimm_bridge_type;
>  extern const struct device_type cxl_nvdimm_type;
> @@ -148,23 +149,19 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
>  #ifdef CONFIG_CXL_RAS
>  int cxl_ras_init(void);
>  void cxl_ras_exit(void);
> -bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base);
> -void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base);
> +bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);
> +void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);
>  #else
>  static inline int cxl_ras_init(void)
>  {
>  	return 0;
>  }
> -
> -static inline void cxl_ras_exit(void)
> -{
> -}
> -
> -static inline bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base)
> +static inline void cxl_ras_exit(void) { }
> +static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
>  {
>  	return false;
>  }
> -static inline void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) { }
> +static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }
>  #endif /* CONFIG_CXL_RAS */
>  
>  /* Restricted CXL Host specific RAS functions */