[PATCH v4 24/28] iommu/arm-smmu-v3-kvm: Shadow STEs

Mostafa Saleh
2025-08-19T21:52:48Z

This patch adds STE emulation, this is done when the host sends the
CFGI_STE command.

In this patch we copy the STE as is to the shadow owned by the hypervisor,
in the next patch, stage-2 page table will be attached.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 95 +++++++++++++++++--
1 file changed, 89 insertions(+), 6 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index d722f8ce0635..0f890a7d8db3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -22,6 +22,9 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
#define strtab_split(smmu) (FIELD_GET(STRTAB_BASE_CFG_SPLIT, (smmu)->host_ste_cfg))
#define strtab_l1_size(smmu) ((1 << (strtab_log2size(smmu) - strtab_split(smmu))) * \
(sizeof(struct arm_smmu_strtab_l1)))
+#define strtab_hyp_base(smmu) ((smmu)->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? \
+ (u64 *)(smmu)->strtab_cfg.l2.l1tab :\
+ (u64 *)(smmu)->strtab_cfg.linear.table)

#define for_each_smmu(smmu) \
for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \
@@ -263,6 +266,83 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}

+/* Get an STE for a stream table base. */
+static struct arm_smmu_ste *smmu_get_ste_ptr(struct hyp_arm_smmu_v3_device *smmu,
+ u32 sid, u64 *strtab)
+{
+ struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
+ struct arm_smmu_ste *table = (struct arm_smmu_ste *)strtab;
+
+ if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
+ struct arm_smmu_strtab_l1 *l1tab = (struct arm_smmu_strtab_l1 *)strtab;
+ u32 l1_idx = arm_smmu_strtab_l1_idx(sid);
+ struct arm_smmu_strtab_l2 *l2ptr;
+
+ if (WARN_ON(l1_idx >= cfg->l2.num_l1_ents) ||
+ !(l1tab[l1_idx].l2ptr & STRTAB_L1_DESC_SPAN))
+ return NULL;
+
+ l2ptr = hyp_phys_to_virt(l1tab[l1_idx].l2ptr & STRTAB_L1_DESC_L2PTR_MASK);
+ /* Two-level walk */
+ return &l2ptr->stes[arm_smmu_strtab_l2_idx(sid)];
+ }
+ if (WARN_ON(sid >= cfg->linear.num_ents))
+ return NULL;
+ return &table[sid];
+}
+
+static int smmu_shadow_l2_strtab(struct hyp_arm_smmu_v3_device *smmu, u32 sid)
+{
+ struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
+ struct arm_smmu_strtab_l2 *l2table;
+ u32 idx = arm_smmu_strtab_l1_idx(sid);
+ u64 *host_ste_base = hyp_phys_to_virt(strtab_host_base(smmu));
+ u64 l1_desc_host = host_ste_base[idx];
+ struct arm_smmu_strtab_l1 *l1_desc = &cfg->l2.l1tab[idx];
+
+ l2table = kvm_iommu_donate_pages(get_order(sizeof(*l2table)));
+ if (!l2table)
+ return -ENOMEM;
+ arm_smmu_write_strtab_l1_desc(l1_desc, hyp_virt_to_phys(l2table));
+ if (!(smmu->features & ARM_SMMU_FEAT_COHERENCY))
+ kvm_flush_dcache_to_poc(l1_desc, sizeof(*l1_desc));
+
+ /*
+ * Now set the hyp l1 to a shared state.
+ * As mentioned in smmu_reshadow_ste() Linux never clears L1 ptrs,
+ * so no need to handle that case. Otherwise, we need to unshare
+ * the tables and emulate STE clear.
+ */
+ smmu_share_pages(l1_desc_host & STRTAB_L1_DESC_L2PTR_MASK, sizeof(*l2table));
+ return 0;
+}
+
+static void smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool leaf)
+{
+ u64 *host_ste_base = hyp_phys_to_virt(strtab_host_base(smmu));
+ u64 *hyp_ste_base = strtab_hyp_base(smmu);
+ struct arm_smmu_ste *host_ste_ptr = smmu_get_ste_ptr(smmu, sid, host_ste_base);
+ struct arm_smmu_ste *hyp_ste_ptr = smmu_get_ste_ptr(smmu, sid, hyp_ste_base);
+ int i;
+
+ /*
+ * Linux only uses leaf = 1, when leaf is 0, we need to verify that this
+ * is a 2 level table and reshadow of l2.
+ * Also Linux never clears l1 ptr, that needs to free the old shadow.
+ */
+ if (WARN_ON(!leaf || !host_ste_ptr))
+ return;
+
+ /* If host is valid and hyp is not, means a new L1 installed. */
+ if (!hyp_ste_ptr) {
+ WARN_ON(smmu_shadow_l2_strtab(smmu, sid));
+ hyp_ste_ptr = smmu_get_ste_ptr(smmu, sid, hyp_ste_base);
+ }
+
+ for (i = 0; i < STRTAB_STE_DWORDS; i++)
+ WRITE_ONCE(hyp_ste_ptr->data[i], host_ste_ptr->data[i]);
+}
+
static int smmu_init_strtab(struct hyp_arm_smmu_v3_device *smmu)
{
int ret;
@@ -390,8 +470,13 @@ static bool smmu_filter_command(struct hyp_arm_smmu_v3_device *smmu, u64 *comman

switch (type) {
case CMDQ_OP_CFGI_STE:
- /* TBD: SHADOW_STE*/
+ {
+ u32 sid = FIELD_GET(CMDQ_CFGI_0_SID, command[0]);
+ u32 leaf = FIELD_GET(CMDQ_CFGI_1_LEAF, command[1]);
+
+ smmu_reshadow_ste(smmu, sid, leaf);
break;
+ }
case CMDQ_OP_CFGI_ALL:
{
/*
@@ -564,23 +649,21 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
regs->regs[rd] = smmu->cmdq_host.llq.cons | err;
}
goto out_ret;
- /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_STRTAB_BASE:
if (is_write) {
/* Must only be written when SMMU_CR0.SMMUEN == 0.*/
WARN_ON(is_smmu_enabled(smmu));
smmu->host_ste_base = val;
}
- mask = read_write;
- break;
+ goto out_ret;
case ARM_SMMU_STRTAB_BASE_CFG:
if (is_write) {
/* Must only be written when SMMU_CR0.SMMUEN == 0.*/
WARN_ON(is_smmu_enabled(smmu));
smmu->host_ste_cfg = val;
}
- mask = read_write;
- break;
+ goto out_ret;
+ /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_GBPA:
mask = read_write;
break;
--
2.51.0.rc1.167.g924127e9c0-goog