[PATCH 10/21] i2c: nomadik: don't use GENMASK()

Yury Norov (NVIDIA)
2025-10-25T16:33:17Z

GENMASK(high, low) notation is confusing. Switch to BITS() or FIRST_BITS()
where appropriate.

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/all/CAHk-=whoOUsqPKb7OQwhQf9H_3=5sXGPJrDbfQfwLB3Bi13tcQ@mail.gmail.com/
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
---
drivers/i2c/busses/i2c-nomadik.c | 44 ++++++++++++++++----------------
1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 19b648fc094d..4c79ada5e1d4 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -53,9 +53,9 @@

/* Control registers */
#define I2C_CR_PE BIT(0) /* Peripheral Enable */
-#define I2C_CR_OM GENMASK(2, 1) /* Operating mode */
+#define I2C_CR_OM BITS(1, 2) /* Operating mode */
#define I2C_CR_SAM BIT(3) /* Slave addressing mode */
-#define I2C_CR_SM GENMASK(5, 4) /* Speed mode */
+#define I2C_CR_SM BITS(4, 5) /* Speed mode */
#define I2C_CR_SGCM BIT(6) /* Slave general call mode */
#define I2C_CR_FTX BIT(7) /* Flush Transmit */
#define I2C_CR_FRX BIT(8) /* Flush Receive */
@@ -63,31 +63,31 @@
#define I2C_CR_DMA_RX_EN BIT(10) /* DMA Rx Enable */
#define I2C_CR_DMA_SLE BIT(11) /* DMA sync. logic enable */
#define I2C_CR_LM BIT(12) /* Loopback mode */
-#define I2C_CR_FON GENMASK(14, 13) /* Filtering on */
-#define I2C_CR_FS GENMASK(16, 15) /* Force stop enable */
+#define I2C_CR_FON BITS(13, 14) /* Filtering on */
+#define I2C_CR_FS BITS(15, 16) /* Force stop enable */

/* Slave control register (SCR) */
-#define I2C_SCR_SLSU GENMASK(31, 16) /* Slave data setup time */
+#define I2C_SCR_SLSU BITS(16, 31) /* Slave data setup time */

/* Master controller (MCR) register */
#define I2C_MCR_OP BIT(0) /* Operation */
-#define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
-#define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
+#define I2C_MCR_A7 BITS(1, 7) /* 7-bit address */
+#define I2C_MCR_EA10 BITS(8, 10) /* 10-bit Extended address */
#define I2C_MCR_SB BIT(11) /* Extended address */
-#define I2C_MCR_AM GENMASK(13, 12) /* Address type */
+#define I2C_MCR_AM BITS(12, 13) /* Address type */
#define I2C_MCR_STOP BIT(14) /* Stop condition */
-#define I2C_MCR_LENGTH GENMASK(25, 15) /* Transaction length */
+#define I2C_MCR_LENGTH BITS(15, 25) /* Transaction length */

/* Status register (SR) */
-#define I2C_SR_OP GENMASK(1, 0) /* Operation */
-#define I2C_SR_STATUS GENMASK(3, 2) /* controller status */
-#define I2C_SR_CAUSE GENMASK(6, 4) /* Abort cause */
-#define I2C_SR_TYPE GENMASK(8, 7) /* Receive type */
-#define I2C_SR_LENGTH GENMASK(19, 9) /* Transfer length */
+#define I2C_SR_OP BITS(0, 1) /* Operation */
+#define I2C_SR_STATUS BITS(2, 3) /* controller status */
+#define I2C_SR_CAUSE BITS(4, 6) /* Abort cause */
+#define I2C_SR_TYPE BITS(7, 8) /* Receive type */
+#define I2C_SR_LENGTH BITS(9, 19) /* Transfer length */

/* Baud-rate counter register (BRCR) */
-#define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */
-#define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */
+#define I2C_BRCR_BRCNT2 FIRST_BITS(16) /* Baud-rate counter 2 */
+#define I2C_BRCR_BRCNT1 BITS(16, 31) /* Baud-rate counter 1 */

/* Interrupt mask set/clear (IMSCR) bits */
#define I2C_IT_TXFE BIT(0)
@@ -339,7 +339,7 @@ static int init_hw(struct nmk_i2c_dev *priv)
#define DEFAULT_I2C_REG_CR (FIELD_PREP(I2C_CR_OM, I2C_OM_MASTER) | I2C_CR_PE)

/* grab top three bits from extended I2C addresses */
-#define ADR_3MSB_BITS GENMASK(9, 7)
+#define ADR_3MSB_BITS BITS(7, 9)

/**
* load_i2c_mcr_reg() - load the MCR register
@@ -1028,11 +1028,11 @@ static void nmk_i2c_of_probe(struct device_node *np,
}

static const unsigned int nmk_i2c_eyeq5_masks[] = {
- GENMASK(5, 4),
- GENMASK(7, 6),
- GENMASK(9, 8),
- GENMASK(11, 10),
- GENMASK(13, 12),
+ BITS(4, 5),
+ BITS(6, 7),
+ BITS(8, 9),
+ BITS(10, 11),
+ BITS(12, 13),
};

static int nmk_i2c_eyeq5_probe(struct nmk_i2c_dev *priv)
--
2.43.0