[PATCH 0/4] i3c: dw: Add support for Device NACK Retry count

[PATCH 0/4] i3c: dw: Add support for Device NACK Retry count

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

This series adds support for configuring the Device NACK Retry count
in the Synopsys DesignWare I3C master controller and enables the
corresponding property in the Altera Agilex5 device tree.

Some I3C slave devices may temporarily NACK transactions when they are
busy or not ready to respond. To enhance bus reliability, the DesignWare
I3C controller supports a programmable retry mechanism that automatically
reissues NACKed transactions. This series introduces the
snps,dev-nack-retry-cnt device tree property to configure this retry
count. The value is written into the Device Address Table (DAT) entry for
each I3C device, enabling fine-grained control of retry behavior.

This series also fixes an issue where existing DAT entries could be
overwritten when the driver restores device addresses. Update
dw_i3c_master_restore_addrs to preserve existing bits in each
DAT entry when restoring addresses.

Adrian Ng Ho Yin (4):
  dt-bindings: i3c: Add snps,dev-nack-retry-cnt property to Synopsys I3C
    master
  arm64: dts: intel: agilex5: Add snps,dev-nack-retry-cnt property for
    I3C controllers
  i3c: dw: Add support for Device NACK Retry count
  i3c: dw: Preserve DAT entry bits when restoring addresses

 .../bindings/i3c/snps,dw-i3c-master.yaml      |  8 ++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  2 +
 drivers/i3c/master/dw-i3c-master.c            | 40 ++++++++++++++++++-
 drivers/i3c/master/dw-i3c-master.h            |  1 +
 4 files changed, 49 insertions(+), 2 deletions(-)

-- 
2.49.GIT

[PATCH 1/4] dt-bindings: i3c: Add snps,dev-nack-retry-cnt property to Synopsys I3C master

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add a new optional property 'snps,dev-nack-retry-cnt' to the Synopsys
DesignWare I3C master device tree binding. This property allows
configuration of the Device NACK Retry count, which determines how many
times the controller retries a transaction when a slave device responds
with NACK.

Valid values range from 0 to 3, with a default of 0

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 .../devicetree/bindings/i3c/snps,dw-i3c-master.yaml       | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index 5f6467375811..c233be2d4a3c 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -37,6 +37,14 @@ properties:
   power-domains:
     maxItems: 1
 
+  snps,dev-nack-retry-cnt:
+    description: |
+      This field is used to set the Device NACK Retry count for the
+      particular slave device.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+    maximum: 3
+
 required:
   - compatible
   - reg
-- 
2.49.GIT

[PATCH 2/4] arm64: dts: intel: agilex5: Add snps,dev-nack-retry-cnt property for I3C controllers

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add the 'snps,dev-nack-retry-cnt' property to the I3C controller nodes
on Agilex5. This configures the Device NACK Retry count for the Synopsys
DesignWare I3C master, allowing it to retry transactions once when a
slave responds with NACK.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 04e99cd7e74b..bb508d092fd6 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -209,6 +209,7 @@ i3c0: i3c@10da0000 {
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+			snps,dev-nack-retry-cnt = <1>;
 			status = "disabled";
 		};
 
@@ -219,6 +220,7 @@ i3c1: i3c@10da1000 {
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+			snps,dev-nack-retry-cnt = <1>;
 			status = "disabled";
 		};
 
-- 
2.49.GIT

[PATCH 3/4] i3c: dw: Add support for Device NACK Retry count

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Some I3C slave devices may temporarily NACK transactions while they are
busy or not ready to respond. To improve bus reliability, the DesignWare
I3C controller provides a mechanism to automatically retry a transaction
when a device issues a NACK.

Add support for configuring the Device NACK Retry count in the Synopsys
DesignWare I3C master driver. The retry count is obtained from the
'snps,dev-nack-retry-cnt' device tree property and written into the
Device Address Table (DAT) entry for each I3C device.

If the property is not defined, the driver defaults to zero retries.
This behavior is consistent across both Device Tree and ACPI-based
systems, where the value is only applied if the corresponding property
is explicitly provided.

The value is clamped to a maximum of 3 (hardware-defined limit), and a
warning is issued if a higher value is specified.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 drivers/i3c/master/dw-i3c-master.c | 34 ++++++++++++++++++++++++++++++
 drivers/i3c/master/dw-i3c-master.h |  1 +
 2 files changed, 35 insertions(+)

diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 9ceedf09c3b6..12ee4c4afedf 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -204,8 +204,10 @@
 #define EXTENDED_CAPABILITY		0xe8
 #define SLAVE_CONFIG			0xec
 
+#define DW_I3C_DEV_NACK_RETRY_CNT_MAX	0x3
 #define DEV_ADDR_TABLE_IBI_MDB		BIT(12)
 #define DEV_ADDR_TABLE_SIR_REJECT	BIT(13)
+#define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x)	(((x) << 29) & GENMASK(30, 29))
 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV	BIT(31)
 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x)	(((x) << 16) & GENMASK(23, 16))
 #define DEV_ADDR_TABLE_STATIC_ADDR(x)	((x) & GENMASK(6, 0))
@@ -989,6 +991,7 @@ static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
 	struct i3c_master_controller *m = i3c_dev_get_master(dev);
 	struct dw_i3c_master *master = to_dw_i3c_master(m);
 	int pos;
+	u32 reg;
 
 	pos = dw_i3c_master_get_free_pos(master);
 
@@ -1009,6 +1012,15 @@ static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
 	       master->regs +
 	       DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
 
+	if (master->dev_nack_retry_cnt) {
+		reg = readl(master->regs +
+			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
+		reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(master->dev_nack_retry_cnt) |
+				DEV_ADDR_TABLE_SIR_REJECT;
+		writel(reg, master->regs +
+			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
+	}
+
 	master->devs[data->index].addr = dev->info.dyn_addr;
 
 	return 0;
@@ -1020,6 +1032,7 @@ static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
 	struct dw_i3c_master *master = to_dw_i3c_master(m);
 	struct dw_i3c_i2c_dev_data *data;
 	int pos;
+	u32 reg;
 
 	pos = dw_i3c_master_get_free_pos(master);
 	if (pos < 0)
@@ -1038,6 +1051,15 @@ static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
 	       master->regs +
 	       DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
 
+	if (master->dev_nack_retry_cnt) {
+		reg = readl(master->regs +
+			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
+		reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(master->dev_nack_retry_cnt) |
+				DEV_ADDR_TABLE_SIR_REJECT;
+		writel(reg, master->regs +
+			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
+	}
+
 	return 0;
 }
 
@@ -1592,6 +1614,18 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
 
 	master->quirks = (unsigned long)device_get_match_data(&pdev->dev);
 
+	ret = device_property_read_u32(&pdev->dev, "snps,dev-nack-retry-cnt",
+				       &master->dev_nack_retry_cnt);
+	if (ret) {
+		master->dev_nack_retry_cnt = 0;
+	} else if (master->dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) {
+		dev_warn(&pdev->dev,
+			 "dev_nack_retry_cnt (%u) exceeds max (%u), clamping to %u\n",
+			 master->dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX,
+			 DW_I3C_DEV_NACK_RETRY_CNT_MAX);
+		master->dev_nack_retry_cnt = DW_I3C_DEV_NACK_RETRY_CNT_MAX;
+	}
+
 	INIT_WORK(&master->hj_work, dw_i3c_hj_work);
 	ret = i3c_master_register(&master->base, &pdev->dev,
 				  &dw_mipi_i3c_ops, false);
diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c-master.h
index c5cb695c16ab..45fc1774724a 100644
--- a/drivers/i3c/master/dw-i3c-master.h
+++ b/drivers/i3c/master/dw-i3c-master.h
@@ -51,6 +51,7 @@ struct dw_i3c_master {
 	u32 i2c_fm_timing;
 	u32 i2c_fmp_timing;
 	u32 quirks;
+	u32 dev_nack_retry_cnt;
 	/*
 	 * Per-device hardware data, used to manage the device address table
 	 * (DAT)
-- 
2.49.GIT

[PATCH 4/4] i3c: dw: Preserve DAT entry bits when restoring addresses

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Update dw_i3c_master_restore_addrs() to preserve existing bits in each
Device Address Table (DAT) entry when restoring addresses. This prevents
overwriting configuration bits during PM runtime resumes.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 drivers/i3c/master/dw-i3c-master.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 12ee4c4afedf..0a9f10677360 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -1688,11 +1688,13 @@ static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master)
 		if (master->free_pos & BIT(pos))
 			continue;
 
+		reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
+
 		if (master->devs[pos].is_i2c_addr)
-			reg_val = DEV_ADDR_TABLE_LEGACY_I2C_DEV |
+			reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV |
 			       DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr);
 		else
-			reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
+			reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
 
 		writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
 	}
-- 
2.49.GIT

Re: [PATCH 1/4] dt-bindings: i3c: Add snps,dev-nack-retry-cnt property to Synopsys I3C master

[Krzysztof Kozlowski]

On 04/11/2025 09:51, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add a new optional property 'snps,dev-nack-retry-cnt' to the Synopsys
> DesignWare I3C master device tree binding. This property allows
> configuration of the Device NACK Retry count, which determines how many
> times the controller retries a transaction when a slave device responds
> with NACK.
> 
> Valid values range from 0 to 3, with a default of 0

Don't explain us the binding. We can read the source code. You miss
rationale what hardware aspect you are solving, why we should accept this.

> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

No, because:
1. Not a board property,
2. Most likely deducible from the compatible,


Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: i3c: Add snps,dev-nack-retry-cnt property to Synopsys I3C master

[Frank Li]

On Tue, Nov 04, 2025 at 04:51:08PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
>
> Add a new optional property 'snps,dev-nack-retry-cnt' to the Synopsys
> DesignWare I3C master device tree binding. This property allows
> configuration of the Device NACK Retry count, which determines how many
> times the controller retries a transaction when a slave device responds
> with NACK.

Look like it is software property, why need put in dt?

Frank

>
> Valid values range from 0 to 3, with a default of 0
>
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  .../devicetree/bindings/i3c/snps,dw-i3c-master.yaml       | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index 5f6467375811..c233be2d4a3c 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -37,6 +37,14 @@ properties:
>    power-domains:
>      maxItems: 1
>
> +  snps,dev-nack-retry-cnt:
> +    description: |
> +      This field is used to set the Device NACK Retry count for the
> +      particular slave device.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0
> +    maximum: 3
> +
>  required:
>    - compatible
>    - reg
> --
> 2.49.GIT
>

Re: [PATCH 3/4] i3c: dw: Add support for Device NACK Retry count

[Frank Li]

On Tue, Nov 04, 2025 at 04:51:10PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
>
> Some I3C slave devices may temporarily NACK transactions while they are
> busy or not ready to respond. To improve bus reliability, the DesignWare
> I3C controller provides a mechanism to automatically retry a transaction
> when a device issues a NACK.
>
> Add support for configuring the Device NACK Retry count in the Synopsys
> DesignWare I3C master driver. The retry count is obtained from the
> 'snps,dev-nack-retry-cnt' device tree property and written into the
> Device Address Table (DAT) entry for each I3C device.

Most like it should come from sys/debugfs interface. Or just fixed value
should be enough.

Frank
>
> If the property is not defined, the driver defaults to zero retries.
> This behavior is consistent across both Device Tree and ACPI-based
> systems, where the value is only applied if the corresponding property
> is explicitly provided.
>
> The value is clamped to a maximum of 3 (hardware-defined limit), and a
> warning is issued if a higher value is specified.
>
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  drivers/i3c/master/dw-i3c-master.c | 34 ++++++++++++++++++++++++++++++
>  drivers/i3c/master/dw-i3c-master.h |  1 +
>  2 files changed, 35 insertions(+)
>
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 9ceedf09c3b6..12ee4c4afedf 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -204,8 +204,10 @@
>  #define EXTENDED_CAPABILITY		0xe8
>  #define SLAVE_CONFIG			0xec
>
> +#define DW_I3C_DEV_NACK_RETRY_CNT_MAX	0x3
>  #define DEV_ADDR_TABLE_IBI_MDB		BIT(12)
>  #define DEV_ADDR_TABLE_SIR_REJECT	BIT(13)
> +#define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x)	(((x) << 29) & GENMASK(30, 29))
>  #define DEV_ADDR_TABLE_LEGACY_I2C_DEV	BIT(31)
>  #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x)	(((x) << 16) & GENMASK(23, 16))
>  #define DEV_ADDR_TABLE_STATIC_ADDR(x)	((x) & GENMASK(6, 0))
> @@ -989,6 +991,7 @@ static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
>  	struct i3c_master_controller *m = i3c_dev_get_master(dev);
>  	struct dw_i3c_master *master = to_dw_i3c_master(m);
>  	int pos;
> +	u32 reg;
>
>  	pos = dw_i3c_master_get_free_pos(master);
>
> @@ -1009,6 +1012,15 @@ static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
>  	       master->regs +
>  	       DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
>
> +	if (master->dev_nack_retry_cnt) {
> +		reg = readl(master->regs +
> +			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
> +		reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(master->dev_nack_retry_cnt) |
> +				DEV_ADDR_TABLE_SIR_REJECT;
> +		writel(reg, master->regs +
> +			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
> +	}
> +
>  	master->devs[data->index].addr = dev->info.dyn_addr;
>
>  	return 0;
> @@ -1020,6 +1032,7 @@ static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
>  	struct dw_i3c_master *master = to_dw_i3c_master(m);
>  	struct dw_i3c_i2c_dev_data *data;
>  	int pos;
> +	u32 reg;
>
>  	pos = dw_i3c_master_get_free_pos(master);
>  	if (pos < 0)
> @@ -1038,6 +1051,15 @@ static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
>  	       master->regs +
>  	       DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
>
> +	if (master->dev_nack_retry_cnt) {
> +		reg = readl(master->regs +
> +			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
> +		reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(master->dev_nack_retry_cnt) |
> +				DEV_ADDR_TABLE_SIR_REJECT;
> +		writel(reg, master->regs +
> +			DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
> +	}
> +
>  	return 0;
>  }
>
> @@ -1592,6 +1614,18 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>
>  	master->quirks = (unsigned long)device_get_match_data(&pdev->dev);
>
> +	ret = device_property_read_u32(&pdev->dev, "snps,dev-nack-retry-cnt",
> +				       &master->dev_nack_retry_cnt);
> +	if (ret) {
> +		master->dev_nack_retry_cnt = 0;
> +	} else if (master->dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) {
> +		dev_warn(&pdev->dev,
> +			 "dev_nack_retry_cnt (%u) exceeds max (%u), clamping to %u\n",
> +			 master->dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX,
> +			 DW_I3C_DEV_NACK_RETRY_CNT_MAX);
> +		master->dev_nack_retry_cnt = DW_I3C_DEV_NACK_RETRY_CNT_MAX;
> +	}
> +
>  	INIT_WORK(&master->hj_work, dw_i3c_hj_work);
>  	ret = i3c_master_register(&master->base, &pdev->dev,
>  				  &dw_mipi_i3c_ops, false);
> diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c-master.h
> index c5cb695c16ab..45fc1774724a 100644
> --- a/drivers/i3c/master/dw-i3c-master.h
> +++ b/drivers/i3c/master/dw-i3c-master.h
> @@ -51,6 +51,7 @@ struct dw_i3c_master {
>  	u32 i2c_fm_timing;
>  	u32 i2c_fmp_timing;
>  	u32 quirks;
> +	u32 dev_nack_retry_cnt;
>  	/*
>  	 * Per-device hardware data, used to manage the device address table
>  	 * (DAT)
> --
> 2.49.GIT
>

Re: [PATCH 0/4] i3c: dw: Add support for Device NACK Retry count

[Alexandre Belloni]

On 04/11/2025 16:51:07+0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> This series adds support for configuring the Device NACK Retry count
> in the Synopsys DesignWare I3C master controller and enables the
> corresponding property in the Altera Agilex5 device tree.
> 
> Some I3C slave devices may temporarily NACK transactions when they are
> busy or not ready to respond. To enhance bus reliability, the DesignWare
> I3C controller supports a programmable retry mechanism that automatically
> reissues NACKed transactions. This series introduces the
> snps,dev-nack-retry-cnt device tree property to configure this retry
> count. The value is written into the Device Address Table (DAT) entry for
> each I3C device, enabling fine-grained control of retry behavior.
> 

As Frank explained, this needs to be a per device sysfs file because
this is definitively policy and not HW related. This file should only be
visible when the bus supports retrying.

Don't forget to add documentation in ABI/testing/sysfs-bus-i3c

> This series also fixes an issue where existing DAT entries could be
> overwritten when the driver restores device addresses. Update
> dw_i3c_master_restore_addrs to preserve existing bits in each
> DAT entry when restoring addresses.
> 
> Adrian Ng Ho Yin (4):
>   dt-bindings: i3c: Add snps,dev-nack-retry-cnt property to Synopsys I3C
>     master
>   arm64: dts: intel: agilex5: Add snps,dev-nack-retry-cnt property for
>     I3C controllers
>   i3c: dw: Add support for Device NACK Retry count
>   i3c: dw: Preserve DAT entry bits when restoring addresses
> 
>  .../bindings/i3c/snps,dw-i3c-master.yaml      |  8 ++++
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  2 +
>  drivers/i3c/master/dw-i3c-master.c            | 40 ++++++++++++++++++-
>  drivers/i3c/master/dw-i3c-master.h            |  1 +
>  4 files changed, 49 insertions(+), 2 deletions(-)
> 
> -- 
> 2.49.GIT
> 

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com