Re: [PATCH v2 2/2] vfio/type1: Set IOMMU_MMIO in dma->prot for MMIO-backed addresses

[Jason Gunthorpe <jgg@nvidia.com>]

On Fri, Nov 07, 2025 at 11:56:51AM -0600, Tom Lendacky wrote:

> When you are on bare-metal, or in the hypervisor, System Memory Encryption
> (SME) deals with the encryption bit set in the page table entries
> (including the nested page table entries for guests). 

So "decrypted" means something about AMD's unique memory encryption
scheme on bare metal but in a CC guest it is a cross arch 'shared with
hypervisor' flag?

What about CXL memory? What about ZONE_DEVICE coherent memory? Do
these get the C bit set too?

:( :( :(

> In the guest (prior to Trusted I/O / TDISP), decrypted (or shared) memory
> is used because a device cannot DMA to or from guest memory using the
> guest encryption key. So all DMA must go to "decrypted" memory or be
> bounce-buffered through "decrypted" memory (SWIOTLB) - basically memory
> that does not get encrypted/decrypted using the guest encryption key.

Where is the code for this? As I wrote we always do sme_set in the
iommu driver, even on guests, even for "decrypted" bounce buffered
memory.

That sounds like a bug by your explanation?

Does this mean vIOMMU has never worked in AMD CC guests?

> It is not until we get to Trusted I/O / TDISP where devices will be able
> to DMA directly to guest encrypted memory and guests will require secure
> MMIO addresses which will need the encryption bit set (Alexey can correct
> me on the TIO statements if they aren't correct, as he is closer to it all).

So in this case we do need to do sme_set on MMIO even though that MMIO
is not using the dram encryption key?

Jason