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From: Alexandre Courbot <acourbot@nvidia.com>
To: "Danilo Krummrich" <dakr@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Benno Lossin" <lossin@kernel.org>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Boqun Feng" <boqun.feng@gmail.com>,
	"Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Trevor Gross" <tmgross@umich.edu>
Cc: John Hubbard <jhubbard@nvidia.com>,
	 Alistair Popple <apopple@nvidia.com>,
	 Joel Fernandes <joelagnelf@nvidia.com>,
	Timur Tabi <ttabi@nvidia.com>,  Edwin Peer <epeer@nvidia.com>,
	nouveau@lists.freedesktop.org,  dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org,  rust-for-linux@vger.kernel.org,
	Alexandre Courbot <acourbot@nvidia.com>
Subject: [PATCH v8 12/16] gpu: nova-core: gsp: Add SetRegistry command
Date: Sat, 08 Nov 2025 08:43:13 +0900	[thread overview]
Message-ID: <20251108-gsp_boot-v8-12-70b762eedd50@nvidia.com> (raw)
In-Reply-To: <20251108-gsp_boot-v8-0-70b762eedd50@nvidia.com>

Add support for sending the SetRegistry command, which is critical to
GSP initialization.

The RM registry is serialized into a packed format and sent via the
command queue. For now only three parameters which are required to boot
GSP are hardcoded. In the future a kernel module parameter will be added
to enable other parameters to be added.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
[acourbot@nvidia.com: split into its own patch.]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
 drivers/gpu/nova-core/gsp/boot.rs                 |  2 +
 drivers/gpu/nova-core/gsp/commands.rs             | 91 +++++++++++++++++++++++
 drivers/gpu/nova-core/gsp/fw/commands.rs          | 50 +++++++++++++
 drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs | 16 ++++
 drivers/gpu/nova-core/sbuffer.rs                  |  1 -
 5 files changed, 159 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs
index b1c1fe77cbf2..dcb5b50e176f 100644
--- a/drivers/gpu/nova-core/gsp/boot.rs
+++ b/drivers/gpu/nova-core/gsp/boot.rs
@@ -158,6 +158,8 @@ pub(crate) fn boot(
 
         self.cmdq
             .send_gsp_command(bar, commands::SetSystemInfo::new(pdev))?;
+        self.cmdq
+            .send_gsp_command(bar, commands::SetRegistry::new())?;
 
         Ok(())
     }
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 091dbe59f655..cc32d4379283 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -1,12 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0
 
+use core::convert::Infallible;
+
 use kernel::device;
 use kernel::pci;
 use kernel::prelude::*;
+use kernel::transmute::AsBytes;
 
 use super::fw::commands::GspSetSystemInfo;
+use super::fw::commands::*;
 use super::fw::MsgFunction;
 use crate::gsp::cmdq::CommandToGsp;
+use crate::sbuffer::SBufferIter;
 
 /// The `GspSetSystemInfo` command.
 pub(crate) struct SetSystemInfo<'a> {
@@ -29,3 +34,89 @@ fn init(&self) -> impl Init<Self::Command, Self::InitError> {
         GspSetSystemInfo::init(self.pdev)
     }
 }
+
+struct RegistryEntry {
+    key: &'static str,
+    value: u32,
+}
+
+/// The `SetRegistry` command.
+pub(crate) struct SetRegistry {
+    entries: [RegistryEntry; Self::NUM_ENTRIES],
+}
+
+impl SetRegistry {
+    // For now we hard-code the registry entries. Future work will allow others to
+    // be added as module parameters.
+    const NUM_ENTRIES: usize = 3;
+
+    /// Creates a new `SetRegistry` command, using a set of hardcoded entries.
+    pub(crate) fn new() -> Self {
+        Self {
+            entries: [
+                // RMSecBusResetEnable - enables PCI secondary bus reset
+                RegistryEntry {
+                    key: "RMSecBusResetEnable",
+                    value: 1,
+                },
+                // RMForcePcieConfigSave - forces GSP-RM to preserve PCI configuration registers on
+                // any PCI reset.
+                RegistryEntry {
+                    key: "RMForcePcieConfigSave",
+                    value: 1,
+                },
+                // RMDevidCheckIgnore - allows GSP-RM to boot even if the PCI dev ID is not found
+                // in the internal product name database.
+                RegistryEntry {
+                    key: "RMDevidCheckIgnore",
+                    value: 1,
+                },
+            ],
+        }
+    }
+}
+
+impl CommandToGsp for SetRegistry {
+    const FUNCTION: MsgFunction = MsgFunction::SetRegistry;
+    type Command = PackedRegistryTable;
+    type InitError = Infallible;
+
+    fn init(&self) -> impl Init<Self::Command, Self::InitError> {
+        PackedRegistryTable::init(Self::NUM_ENTRIES as u32, self.variable_payload_len() as u32)
+    }
+
+    fn variable_payload_len(&self) -> usize {
+        let mut key_size = 0;
+        for i in 0..Self::NUM_ENTRIES {
+            key_size += self.entries[i].key.len() + 1; // +1 for NULL terminator
+        }
+        Self::NUM_ENTRIES * size_of::<PackedRegistryEntry>() + key_size
+    }
+
+    fn init_variable_payload(
+        &self,
+        dst: &mut SBufferIter<core::array::IntoIter<&mut [u8], 2>>,
+    ) -> Result {
+        let string_data_start_offset =
+            size_of::<PackedRegistryTable>() + Self::NUM_ENTRIES * size_of::<PackedRegistryEntry>();
+
+        // Array for string data.
+        let mut string_data = KVec::new();
+
+        for entry in self.entries.iter().take(Self::NUM_ENTRIES) {
+            dst.write_all(
+                PackedRegistryEntry::new(
+                    (string_data_start_offset + string_data.len()) as u32,
+                    entry.value,
+                )
+                .as_bytes(),
+            )?;
+
+            let key_bytes = entry.key.as_bytes();
+            string_data.extend_from_slice(key_bytes, GFP_KERNEL)?;
+            string_data.push(0, GFP_KERNEL)?;
+        }
+
+        dst.write_all(string_data.as_slice())
+    }
+}
diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-core/gsp/fw/commands.rs
index 0d3c46f793dd..e5aab4032175 100644
--- a/drivers/gpu/nova-core/gsp/fw/commands.rs
+++ b/drivers/gpu/nova-core/gsp/fw/commands.rs
@@ -54,3 +54,53 @@ unsafe impl AsBytes for GspSetSystemInfo {}
 // SAFETY: These structs don't meet the no-padding requirements of FromBytes but
 //         that is not a problem because they are not used outside the kernel.
 unsafe impl FromBytes for GspSetSystemInfo {}
+
+#[repr(transparent)]
+pub(crate) struct PackedRegistryEntry(bindings::PACKED_REGISTRY_ENTRY);
+
+impl PackedRegistryEntry {
+    pub(crate) fn new(offset: u32, value: u32) -> Self {
+        Self({
+            bindings::PACKED_REGISTRY_ENTRY {
+                nameOffset: offset,
+
+                // We only support DWORD types for now. Support for other types
+                // will come later if required.
+                type_: bindings::REGISTRY_TABLE_ENTRY_TYPE_DWORD as u8,
+                __bindgen_padding_0: Default::default(),
+                data: value,
+                length: 0,
+            }
+        })
+    }
+}
+
+// SAFETY: Padding is explicit and will not contain uninitialized data.
+unsafe impl AsBytes for PackedRegistryEntry {}
+
+/// Payload of the `SetRegistry` command.
+#[repr(transparent)]
+pub(crate) struct PackedRegistryTable {
+    inner: bindings::PACKED_REGISTRY_TABLE,
+}
+
+impl PackedRegistryTable {
+    #[allow(non_snake_case)]
+    pub(crate) fn init(num_entries: u32, size: u32) -> impl Init<Self> {
+        type InnerPackedRegistryTable = bindings::PACKED_REGISTRY_TABLE;
+        let init_inner = init!(InnerPackedRegistryTable {
+            numEntries: num_entries,
+            size,
+            entries: Default::default()
+        });
+
+        init!(PackedRegistryTable { inner <- init_inner })
+    }
+}
+
+// SAFETY: Padding is explicit and will not contain uninitialized data.
+unsafe impl AsBytes for PackedRegistryTable {}
+
+// SAFETY: This struct only contains integer types for which all bit patterns
+// are valid.
+unsafe impl FromBytes for PackedRegistryTable {}
diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs
index 1251b0c313ce..32933874ff97 100644
--- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs
+++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs
@@ -649,6 +649,22 @@ pub struct LibosMemoryRegionInitArgument {
     pub __bindgen_padding_0: [u8; 6usize],
 }
 #[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct PACKED_REGISTRY_ENTRY {
+    pub nameOffset: u32_,
+    pub type_: u8_,
+    pub __bindgen_padding_0: [u8; 3usize],
+    pub data: u32_,
+    pub length: u32_,
+}
+#[repr(C)]
+#[derive(Debug, Default)]
+pub struct PACKED_REGISTRY_TABLE {
+    pub size: u32_,
+    pub numEntries: u32_,
+    pub entries: __IncompleteArrayField<PACKED_REGISTRY_ENTRY>,
+}
+#[repr(C)]
 #[derive(Debug, Default, Copy, Clone, Zeroable)]
 pub struct msgqTxHeader {
     pub version: u32_,
diff --git a/drivers/gpu/nova-core/sbuffer.rs b/drivers/gpu/nova-core/sbuffer.rs
index 57153c1c3515..deb9c1469a95 100644
--- a/drivers/gpu/nova-core/sbuffer.rs
+++ b/drivers/gpu/nova-core/sbuffer.rs
@@ -198,7 +198,6 @@ fn get_slice_mut(&mut self, len: usize) -> Option<&'a mut [u8]> {
 
     /// Ideally we would implement [`Write`], but it is not available in `core`.
     /// So mimic `std::io::Write::write_all`.
-    #[expect(unused)]
     pub(crate) fn write_all(&mut self, mut src: &[u8]) -> Result {
         while !src.is_empty() {
             match self.get_slice_mut(src.len()) {

-- 
2.51.2


  parent reply	other threads:[~2025-11-07 23:44 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-07 23:43 [PATCH v8 00/16] gpu: nova-core: Boot GSP to RISC-V active Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 01/16] gpu: nova-core: compute layout of more framebuffer regions required for GSP Alexandre Courbot
2025-11-14 21:53   ` Lyude Paul
2025-11-17 11:30     ` Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 02/16] gpu: nova-core: Set correct DMA mask Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 03/16] gpu: nova-core: num: add functions to safely convert a const value to a smaller type Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 04/16] gpu: nova-core: Create initial Gsp Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 05/16] gpu: nova-core: gsp: Create wpr metadata Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 06/16] gpu: nova-core: Add a slice-buffer (sbuffer) datastructure Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 07/16] gpu: nova-core: Add zeroable trait to bindings Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 08/16] rust: enable slice_flatten feature and provide it through an extension trait Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 09/16] gpu: nova-core: gsp: Add GSP command queue bindings and handling Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 10/16] gpu: nova-core: gsp: Create rmargs Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 11/16] gpu: nova-core: gsp: Add SetSystemInfo command Alexandre Courbot
2025-11-07 23:43 ` Alexandre Courbot [this message]
2025-11-07 23:43 ` [PATCH v8 13/16] gpu: nova-core: falcon: Add support to check if RISC-V is active Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 14/16] gpu: nova-core: falcon: Add support to write firmware version Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 15/16] gpu: nova-core: gsp: Boot GSP Alexandre Courbot
2025-11-07 23:43 ` [PATCH v8 16/16] bitfields RANGE doc - not great Alexandre Courbot
2025-11-08  0:10   ` Alexandre Courbot
2025-11-08  2:51 ` [PATCH v8 00/16] gpu: nova-core: Boot GSP to RISC-V active Alexandre Courbot

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