Re: [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement

Alison Schofield
2025-11-04T16:17:26Z

On Mon, Nov 03, 2025 at 07:47:41PM +0100, Robert Richter wrote:
> This patch set adds support for address translation using ACPI PRM and
> enables this for AMD Zen5 platforms. This is another new appoach in
> response to earlier attempts to implement CXL address translation:
>
> * v1: [1] and the comments on it, esp. Dan's [2],
> * v2: [3] and comments on [4], esp. Dave's [5]
> * v3: [6] and comments on it, esp. Dave's [7]
>
> This version 4 reworks and simplifies code to use an address
> translation callback bound to the root port. It moves all address
> translation code to a single file, core/atl.c.
>
> Documentation of CXL Address Translation Support will be added to the
> Kernel's "Compute Express Link: Linux Conventions". This patch
> submission will be the base for a documention patch that describes CXL
> Address Translation support accordingly.

Hi Robert,

I see above that the documentation is expected to follow this patchset.
I'd been holding off expecting to have that in hand to do a decent
review here. Is that doc not necessary for review? Do commit messages,
code comments, and spec references give reviewers all they need?

>
> The CXL driver currently does not implement address translation which
> assumes the host physical addresses (HPA) and system physical
> addresses (SPA) are equal.
>
> Systems with different HPA and SPA addresses need address translation.
> If this is the case, the hardware addresses esp. used in the HDM
> decoder configurations are different to the system's or parent port
> address ranges. E.g. AMD Zen5 systems may be configured to use
> 'Normalized addresses'. Then, CXL endpoints have their own physical
> address base which is not the same as the SPA used by the CXL host
> bridge. Thus, addresses need to be translated from the endpoint's to
> its CXL host bridge's address range.
>
> To enable address translation, the endpoint's HPA range must be
> translated to the CXL host bridge's address range. A callback is
> introduced to translate a decoder's HPA to the CXL host bridge's
> address range. The callback is then used to determine the region
> parameters which includes the SPA translated address range of the
> endpoint decoder and the interleaving configuration. This is stored in
> struct cxl_region which allows an endpoint decoder to determine that
> parameters based on its assigned region.
>
> Note that only auto-discovery of decoders is supported. Thus, decoders
> are locked and cannot be configured manually.
>
> Finally, Zen5 address translation is enabled using ACPI PRMT.
>
> There are 3 additional cleanup patches at the end of the series. It
> might be worth to add them too, but could be dropped if there are
> concerns.

I peeked at the 3 trailing patches and they don't seem to depend upon
the series. I'd suggest submitting those individually for review.
That'll pull in more reviewers to those, ie folks who might not jump
into the entire patchset.

Thanks!
Alison

>
> This series bases on cxl/next.
>
> V4:
> * rebased onto v6.18-rc2 (cxl/next),
> * updated sob-chain,
> * reworked and simplified code to use an address translation callback
> bound to the root port,
> * moved all address translation code to core/atl.c,
> * cxlr->cxlrd change, updated patch description (Alison),
> * use DEFINE_RANGE() (Jonathan),
> * change name to @hpa_range (Dave, Jonathan),
> * updated patch description if there is a no-op (Gregory),
> * use Designated initializers for struct cxl_region_context (Dave),
> * move callback handler to struct cxl_root_ops (Dave),
> * move hanler inialization to acpi_probe() (Dave),
> * updated comment where Normalized Addressing is checked (Dave),
> * limit PRM enablement only to AMD supported kernel configs (AMD_NB)
> (Jonathan),
> * added 3 related optional cleanup patches at the end of the series,
>
> V3:
> * rebased onto cxl/next,
> * complete rework to reduce number of required changes/patches and to
> remove platform specific code (Dan and Dave),
> * changed implementation allowing to add address translation to the
> CXL specification (documention patch in preparation),
> * simplified and generalized determination of interleaving
> parameters using the address translation callback,
> * depend only on the existence of the ACPI PRM GUID for CXL Address
> Translation enablement, removed platform checks,
> * small changes to region code only which does not require a full
> rework and refactoring of the code, just separating region
> parameter setup and region construction,
> * moved code to new core/atl.c file,
> * fixed subsys_initcall order dependency of EFI runtime services
> (Gregory and Joshua),
>
> V2:
> * rebased onto cxl/next,
> * split of v1 in two parts:
> * removed cleanups and updates from this series to post them as a
> separate series (Dave),
> * this part 2 applies on top of part 1, v3,
> * added tags to SOB chain,
> * reworked architecture, vendor and platform setup (Jonathan):
> * added patch "cxl/x86: Prepare for architectural platform setup",
> * added function arch_cxl_port_platform_setup() plus a __weak
> versions for archs other than x86,
> * moved code to core/x86,
> * added comment to cxl_to_hpa_fn (Ben),
> * updated year in copyright statement (Ben),
> * cxl_port_calc_hpa(): Removed HPA check for zero (Jonathan), return
> 1 if modified,
> * cxl_port_calc_pos(): Updated description and wording (Ben),
> * added sereral patches around interleaving and SPA calculation in
> cxl_endpoint_decoder_initialize(),
> * reworked iterator in cxl_endpoint_decoder_initialize() (Gregory),
> * fixed region interleaving parameters() (Alison),
> * fixed check in cxl_region_attach() (Alison),
> * Clarified in coverletter that not all ports in a system must
> implement the to_hpa() callback (Terry).
>
> [1] https://lore.kernel.org/linux-cxl/20240701174754.967954-1-rrichter@amd.com/
> [2] https://lore.kernel.org/linux-cxl/669086821f136_5fffa29473@dwillia2-xfh.jf.intel.com.notmuch/
> [3] https://patchwork.kernel.org/project/cxl/cover/20250218132356.1809075-1-rrichter@amd.com/
> [4] https://patchwork.kernel.org/project/cxl/cover/20250715191143.1023512-1-rrichter@amd.com/
> [5] https://lore.kernel.org/all/78284b12-3e0b-4758-af18-397f32136c3f@intel.com/
> [6] https://patchwork.kernel.org/project/cxl/cover/20250912144514.526441-1-rrichter@amd.com/
> [7] https://lore.kernel.org/all/20250912144514.526441-8-rrichter@amd.com/T/#m23c2adb9d1e20770ccd5d11475288bda382b0af5
>
> Robert Richter (14):
> cxl/region: Store root decoder in struct cxl_region
> cxl/region: Store HPA range in struct cxl_region
> cxl/region: Rename misleading variable name @hpa to @hpa_range
> cxl/region: Add @hpa_range argument to function
> cxl_calc_interleave_pos()
> cxl: Simplify cxl_root_ops allocation and handling
> cxl/region: Separate region parameter setup and region construction
> cxl/region: Use region data to get the root decoder
> cxl: Introduce callback for HPA address ranges translation
> cxl/acpi: Prepare use of EFI runtime services
> cxl: Enable AMD Zen5 address translation using ACPI PRMT
> cxl/atl: Lock decoders that need address translation
> cxl: Simplify cxl_rd_ops allocation and handling
> cxl/acpi: Group xor arithmetric setup code in a single block
> cxl/region: Remove local variable @inc in cxl_port_setup_targets()
>
> drivers/cxl/Kconfig | 4 +
> drivers/cxl/acpi.c | 32 +++---
> drivers/cxl/core/Makefile | 1 +
> drivers/cxl/core/atl.c | 205 ++++++++++++++++++++++++++++++++++++++
> drivers/cxl/core/cdat.c | 8 +-
> drivers/cxl/core/core.h | 9 ++
> drivers/cxl/core/port.c | 9 +-
> drivers/cxl/core/region.c | 185 +++++++++++++++++++---------------
> drivers/cxl/cxl.h | 33 ++++--
> 9 files changed, 366 insertions(+), 120 deletions(-)
> create mode 100644 drivers/cxl/core/atl.c
>
>
> base-commit: 211ddde0823f1442e4ad052a2f30f050145ccada
> --
> 2.47.3
>
>