From: Jason Gunthorpe <jgg@nvidia.com>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Kevin Tian <kevin.tian@intel.com>,
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] iommu/vt-d: Restore previous domain::aperture_end calculation
Date: Thu, 20 Nov 2025 09:00:45 -0400 [thread overview]
Message-ID: <20251120130045.GB153257@nvidia.com> (raw)
In-Reply-To: <20251120072524.3218282-1-baolu.lu@linux.intel.com>
On Thu, Nov 20, 2025 at 03:25:24PM +0800, Lu Baolu wrote:
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -2817,6 +2817,16 @@ intel_iommu_domain_alloc_first_stage(struct device *dev,
> cfg.common.hw_max_vasz_lg2 = 57;
> else
> cfg.common.hw_max_vasz_lg2 = 48;
> +
> + /*
> + * Spec 3.6 First-Stage Translation:
> + *
> + * Software must limit addresses to less than the minimum of MGAW
> + * and the lower canonical address width implied by FSPM (i.e.,
> + * 47-bit when FSPM is 4-level and 56-bit when FSPM is 5-level).
> + */
> + cfg.common.hw_max_vasz_lg2 = min(cap_mgaw(iommu->cap),
> + cfg.common.hw_max_vasz_lg2);
> cfg.common.hw_max_oasz_lg2 = 52;
> cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |
> BIT(PT_FEAT_FLUSH_RANGE);
This is missing the hunk for paging_domain_compatible_first_stage(), I
think that is important!
Jason
next prev parent reply other threads:[~2025-11-20 13:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 7:25 [PATCH 1/1] iommu/vt-d: Restore previous domain::aperture_end calculation Lu Baolu
2025-11-20 10:35 ` Joerg Roedel
2025-11-20 13:00 ` Jason Gunthorpe [this message]
2025-11-21 1:39 ` Baolu Lu
2025-11-21 7:30 ` Tian, Kevin
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