Re: [PATCH v4 0/9] dax/hmem, cxl: Coordinate Soft Reserved handling with CXL and HMEM

Tomasz Wolski
2025-12-05T23:04:13Z

Hello Dan & Gotou-san,

Many thanks for your remarks for the test cases
For the qemu tests I used modified qemu and sebios, therefore some 'strange' cases
are only testable on virtual setups - thanks for making it clear which configurations
are supported in real life

>>
>> [4] Physical machine: 2 CFMWS + Host-bridge + 2 CXL devices
>>
>> kernel: BIOS-e820: [mem 0x0000002070000000-0x000000a06fffffff] soft
>> reserved
>>
>> 2070000000-606fffffff : CXL Window 0
>> 2070000000-606fffffff : region0
>> 2070000000-606fffffff : dax0.0
>> 2070000000-606fffffff : System RAM (kmem) 6070000000-a06fffffff
>> : CXL Window 1
>> 6070000000-a06fffffff : region1
>> 6070000000-a06fffffff : dax1.0
>> 6070000000-a06fffffff : System RAM (kmem)
>
>Ok, so a real world maching that creates a merged 0x0000002070000000-0x000000a06fffffff range. Can you confirm that the SRAT has separate entries for those ranges? >Otherwise, need to rethink how to keep this fallback algorithm simple and predictable.

I looked into the syslogs and I see the SRAT has separate entries:

[ 0.005128] [ T0] ACPI: SRAT: Node 2 PXM 2 [mem 0x2070000000-0x606fffffff] hotplug
[ 0.005129] [ T0] ACPI: SRAT: Node 2 PXM 2 [mem 0x6070000000-0xa06fffffff] hotplug