From: Jason Gunthorpe <jgg@ziepe.ca>
To: Sairaj Kodilkar <sarunkod@amd.com>
Cc: joro@8bytes.org, suravee.suthikulpanit@amd.com, will@kernel.org,
robin.murphy@arm.com, kevin.tian@intel.com,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
vasant.hegde@amd.com
Subject: Re: [RFC PATCH] iommu/amd: Add control register in `struct iommu_hw_info_amd`
Date: Fri, 21 Nov 2025 19:35:45 -0400 [thread overview]
Message-ID: <20251121233545.GJ233636@ziepe.ca> (raw)
In-Reply-To: <20251029095846.4486-1-sarunkod@amd.com>
On Wed, Oct 29, 2025 at 03:28:46PM +0530, Sairaj Kodilkar wrote:
> When user does IOMMU_GET_HW_INFO ioctl, read the IOMMU control
> register (MMIO offset 0x0018) and return it as part of
> `struct iommu_hw_info_amd`.
>
> Userspace can use this information to determine the features
> supported by the underlying host kernel.
>
> Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
> ---
>
> The patch exposes the control register to the user space so that QEMU
> can determine the list of features enabled by the host IOMMU driver
> when there are passthrough devices. QEMU can use this information to
> selectively enable the guest feature. One example of such feature is
> enabling upto 2048 MSIs for passthrough devices. QEMU must not enable
> this feature for passthrough devices when host IOMMU driver has not
> enabled it.
Please document in the uapi header what bits are meaningful and
userspace can safely access..
You are OK that a 0 register means the kernel is old?
Jason
next prev parent reply other threads:[~2025-11-21 23:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 9:58 [RFC PATCH] iommu/amd: Add control register in `struct iommu_hw_info_amd` Sairaj Kodilkar
2025-11-21 23:35 ` Jason Gunthorpe [this message]
2025-11-26 5:07 ` Sairaj Kodilkar
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