From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailtransmit04.runbox.com (mailtransmit04.runbox.com [185.226.149.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 374742D9EC9 for ; Tue, 25 Nov 2025 09:35:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.226.149.37 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764063350; cv=none; b=uLlHJQPY8mjqQzMTItE3gMXaEz12pHSwZo0DTovxN/RZDY5ytULqPc1bBRYQKKnKCbIEeXCuIaCTudIrbUuhperc7vh9lWTEViV+WF4PC62tX691YzV10GZlpPaGio/YON3Q7u+reAL90+7Kbhx9P+LsNrHhcIyKWBs30+e0wsg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764063350; c=relaxed/simple; bh=U7nEComjY2e2YunGcczdvtjizwqqMhv4CrkgLh/axMc=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mNVflZQL2LauUtNfY0rkJqcj63ftjgtszfcBg5Vci8XbJN1zDaOOQJU/jY2O8IuX9NNXRipXdvS56h3x2gfCeeMxwVGuNcUdPSYNd3PloUpePmicfYGgvFd+p0aTCfI8h6Nqcwr6Thd8Arsv3gM5LHPLDHNflUKFkySKg4OcvsI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=runbox.com; spf=pass smtp.mailfrom=runbox.com; dkim=pass (2048-bit key) header.d=runbox.com header.i=@runbox.com header.b=tWLXEd2O; arc=none smtp.client-ip=185.226.149.37 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=runbox.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=runbox.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=runbox.com header.i=@runbox.com header.b="tWLXEd2O" Received: from mailtransmit03.runbox ([10.9.9.163] helo=aibo.runbox.com) by mailtransmit04.runbox.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1vNpSR-005rs2-IL; Tue, 25 Nov 2025 10:35:35 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=runbox.com; s=selector1; h=Content-Transfer-Encoding:Content-Type:MIME-Version: References:In-Reply-To:Message-ID:Subject:Cc:To:From:Date; bh=9C9j2EwP+dfCKYDGUnBZKucdfkkvyKBJa+crvY0pd3Q=; b=tWLXEd2OfSPBUqTTSDCMALSLb9 CB0121g6ZahaJLbG7XnJTz7kyuyUILWbHQHKyofFVC46/uzIL8d7aZiLj2bNe7HPr9oIHVS4qU+/c ++XSu2r/kpGtbTfdMbWh3G2c01GgIUGuNb3mgvZKVeR4xE/HTygrAiP5WgnmWd/gXMWabftfO1by2 FAPULHEnkWjX/+nlebIMxfK+nmb1kEiM2stWFD6UZDXsqiI8s857lygwZrHGKuy1UskuyqY1UKn1e d7e5QmHCM04KL4zIbJRDKNX7u6SB61RuO6YCmnRuOXIa1vIQ3+zZMe9lYhytf52zrfX9QKdJuO65m Z3T2+9bQ==; Received: from [10.9.9.73] (helo=submission02.runbox) by mailtransmit03.runbox with esmtp (Exim 4.86_2) (envelope-from ) id 1vNpSR-0003qd-1E; Tue, 25 Nov 2025 10:35:35 +0100 Received: by submission02.runbox with esmtpsa [Authenticated ID (1493616)] (TLS1.2:ECDHE_SECP256R1__RSA_SHA256__AES_256_GCM:256) (Exim 4.93) id 1vNpSQ-00Bj0C-0q; Tue, 25 Nov 2025 10:35:34 +0100 Date: Tue, 25 Nov 2025 09:35:29 +0000 From: david laight To: Nikolay Borisov Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, Yazen.Ghannam@amd.com Subject: Re: [PATCH v2] RAS/AMD/ATL: Remove bitwise_xor_bits Message-ID: <20251125093529.109c8e1e@pumpkin> In-Reply-To: <20251124084011.1575166-1-nik.borisov@suse.com> References: <20251124084011.1575166-1-nik.borisov@suse.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 24 Nov 2025 10:40:11 +0200 Nikolay Borisov wrote: > Both LLVM/GCC support a __builtin_parity function which is functionally > equivalent to the custom bitwise_xor_bits() one. Let's simplify the code by > relying on the built-in. No functional changes. > While you've got this code out on the operating table: - Change all the locals/parameters from u8/u16 to 'unsigned int'. It will generate better code. Using u8/u16 only makes any sense if you are trying to reduce the size of a structure. - Both col_xor and row_xor are masks (for the parity code). So the names are wrong. In fact I think all the 'xor' and 'XOR' are incorrectly named. - How often is 'xor_enable' aka 'mask_enable' set? If set most of the time (or the code rarely runs) then if the hardware register says 'don't include these values' then just set the row/col mask values to zero and let the rest of the code just run through. David