[PATCH 0/2] Add support for configuring pin properties on RZ/T2H-N2H SoCs

[PATCH 0/2] Add support for configuring pin properties on RZ/T2H-N2H SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi all,

This patch series adds support for configuring pin properties on the
Renesas RZ/T2H-N2H SoCs. The RZ/T2H allows configuring pin properties
through the DRCTLm (I/O Buffer Function Switching) registers, including:
- Drive strength (low/middle/high/ultra high)
- Pull-up/pull-down/no-bias configuration (3 options: no pull, pull-up,
  pull-down)
- Schmitt trigger control (enable/disable)
- Slew rate control (2 options: slow/fast)

Cheers,
Prabhakar 

Lad Prabhakar (2):
  dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration
    properties
  pinctrl: renesas: rzt2h: Add pin configuration support

 .../pinctrl/renesas,r9a09g077-pinctrl.yaml    |  13 +
 drivers/pinctrl/renesas/pinctrl-rzt2h.c       | 230 ++++++++++++++++++
 2 files changed, 243 insertions(+)

-- 
2.43.0

[PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the pin configuration properties supported by the RZ/T2H pinctrl
driver. The RZ/T2H SoC supports configuring various electrical properties
through the DRCTLm (I/O Buffer Function Switching) registers.

Add documentation for the following standard properties:
- bias-disable, bias-pull-up, bias-pull-down: Control internal
  pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
- input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
  input
- slew-rate: Control output slew rate (2 options: slow/fast)

Add documentation for the custom property:
- renesas,drive-strength: Control output drive strength using discrete
  levels (0-3) representing low, medium, high, and ultra high strength.
  This custom property is needed because the hardware uses fixed discrete
  levels rather than configurable milliamp values.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
index 36d665971484..9085d5cfb1c8 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
@@ -72,6 +72,19 @@ definitions:
       input: true
       input-enable: true
       output-enable: true
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      input-schmitt-enable: true
+      input-schmitt-disable: true
+      slew-rate:
+        enum: [0, 1]
+      renesas,drive-strength:
+        description:
+          Drive strength configuration value. Valid values are 0 to 3, representing
+          increasing drive strength from low, medium, high and ultra high.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [0, 1, 2, 3]
     oneOf:
       - required: [pinmux]
       - required: [pins]
-- 
2.43.0

[PATCH 2/2] pinctrl: renesas: rzt2h: Add pin configuration support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H allows
configuring pin properties through the DRCTLm (I/O Buffer Function
Switching) registers, including:
- Drive strength (low/middle/high/ultra high)
- Pull-up/pull-down/no-bias configuration (3 options: no pull, pull-up,
  pull-down)
- Schmitt trigger control (enable/disable)
- Slew rate control (2 options: slow/fast)

The drive strength configuration uses four discrete levels (low, middle,
high, ultra high) rather than the standard milliamp values. To properly
represent this hardware behavior, implement a custom device-tree binding
parameter "renesas,drive-strength" that accepts values 0-3 corresponding
to these discrete levels.

The DRCTLm registers are accessed in 32-bit mode, with each port split
into two halves (bits 0-3 and bits 4-7) requiring separate register
offsets.

Implement pinconf_ops to support:
- Getting/setting individual pin configurations
- Getting/setting pin group configurations
- Standard properties: bias-disable, bias-pull-up, bias-pull-down,
  input-schmitt-enable, slew-rate
- Custom property: renesas,drive-strength

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzt2h.c | 230 ++++++++++++++++++++++++
 1 file changed, 230 insertions(+)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
index 4826ff91cd90..501b05844046 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
@@ -42,16 +42,27 @@
 #define PMC(m)		(0x400 + (m))
 #define PFC(m)		(0x600 + 8 * (m))
 #define PIN(m)		(0x800 + (m))
+#define DRCTL(n)	(0xa00 + 0x008 * (n))
 #define RSELP(m)	(0xc00 + (m))
 
 #define PM_MASK			GENMASK(1, 0)
 #define PM_PIN_MASK(pin)	(PM_MASK << ((pin) * 2))
 #define PM_INPUT		BIT(0)
 #define PM_OUTPUT		BIT(1)
+#define SR_MASK			0x01
+#define SCHMITT_MASK		0x01
+#define IOLH_MASK		0x03
+#define PUPD_MASK		0x03
 
 #define PFC_MASK		GENMASK_ULL(5, 0)
 #define PFC_PIN_MASK(pin)	(PFC_MASK << ((pin) * 8))
 
+#define DRCTL_BIT_OFFSET(bit)		((bit) * 8)
+#define DRCTL_IOLH_SHIFT(bit)		DRCTL_BIT_OFFSET(bit)
+#define DRCTL_PUPD_SHIFT(bit)		(DRCTL_BIT_OFFSET(bit) + 2)
+#define DRCTL_SCHMITT_SHIFT(bit)	(DRCTL_BIT_OFFSET(bit) + 4)
+#define DRCTL_SR_SHIFT(bit)		(DRCTL_BIT_OFFSET(bit) + 5)
+
 /*
  * Use 16 lower bits [15:0] for pin identifier
  * Use 8 higher bits [23:16] for pin mux function
@@ -101,8 +112,22 @@ static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port
 
 RZT2H_PINCTRL_REG_ACCESS(b, u8)
 RZT2H_PINCTRL_REG_ACCESS(w, u16)
+RZT2H_PINCTRL_REG_ACCESS(l, u32)
 RZT2H_PINCTRL_REG_ACCESS(q, u64)
 
+/* Custom pinconf parameters */
+#define RENESAS_RZT2H_PIN_CONFIG_DRIVE_STRENGTH		(PIN_CONFIG_END + 1)
+
+static const struct pinconf_generic_params renesas_rzt2h_custom_bindings[] = {
+	{"renesas,drive-strength", RENESAS_RZT2H_PIN_CONFIG_DRIVE_STRENGTH, 0},
+};
+
+#ifdef CONFIG_DEBUG_FS
+static const struct pin_config_item renesas_rzt2h_conf_items[] = {
+	PCONFDUMP(RENESAS_RZT2H_PIN_CONFIG_DRIVE_STRENGTH, "drive-strength", NULL, true),
+};
+#endif
+
 static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
 {
 	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
@@ -425,6 +450,196 @@ static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev,
 	return ret;
 }
 
+static int rzt2h_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
+				     unsigned int _pin,
+				     unsigned long *config)
+{
+	struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	u32 param = pinconf_to_config_param(*config);
+	u32 port = RZT2H_PIN_ID_TO_PORT(_pin);
+	u8 bit = RZT2H_PIN_ID_TO_PIN(_pin);
+	u32 addr = DRCTL(port);
+	unsigned int arg;
+	int ret;
+
+	ret = rzt2h_validate_pin(pctrl, _pin);
+	if (ret)
+		return ret;
+
+	/* Access DRCTLm register in 32-bit mode */
+	if (bit >= 4) {
+		bit -= 4;
+		addr += 4;
+	}
+
+	arg = rzt2h_pinctrl_readl(pctrl, port, addr);
+
+	switch (param) {
+	case PIN_CONFIG_SLEW_RATE:
+		 arg = (arg >> DRCTL_SR_SHIFT(bit)) & SR_MASK;
+		break;
+
+	case PIN_CONFIG_BIAS_DISABLE:
+	case PIN_CONFIG_BIAS_PULL_UP:
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		 arg = (arg >> DRCTL_PUPD_SHIFT(bit)) & PUPD_MASK;
+		if ((arg == 0 && param != PIN_CONFIG_BIAS_DISABLE) ||
+		    (arg == 0x1 && param != PIN_CONFIG_BIAS_PULL_UP) ||
+		    (arg == 0x2 && param != PIN_CONFIG_BIAS_PULL_DOWN))
+			return -EINVAL;
+		break;
+
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		arg = (arg >> DRCTL_SCHMITT_SHIFT(bit)) & SCHMITT_MASK;
+		if (!arg)
+			return -EINVAL;
+		break;
+
+	case RENESAS_RZT2H_PIN_CONFIG_DRIVE_STRENGTH:
+		arg = (arg >> DRCTL_IOLH_SHIFT(bit)) & IOLH_MASK;
+		break;
+
+	default:
+		return -ENOTSUPP;
+	}
+
+	*config = pinconf_to_config_packed(param, arg);
+
+	return 0;
+};
+
+static void rzt2h_drctl_rmw(struct rzt2h_pinctrl *pctrl, unsigned int pin,
+			    u32 mask, u32 val)
+{
+	u32 port = RZT2H_PIN_ID_TO_PORT(pin);
+	u8 bit = RZT2H_PIN_ID_TO_PIN(pin);
+	u32 offset = DRCTL(port);
+	unsigned long flags;
+	u32 drctl;
+
+	/* Access DRCTLm register in 32-bit mode */
+	if (bit >= 4)
+		offset += 4;
+
+	spin_lock_irqsave(&pctrl->lock, flags);
+	drctl = rzt2h_pinctrl_readl(pctrl, port, offset) & ~mask;
+	rzt2h_pinctrl_writel(pctrl, port, drctl | val, offset);
+	spin_unlock_irqrestore(&pctrl->lock, flags);
+}
+
+static int rzt2h_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
+				     unsigned int _pin,
+				     unsigned long *_configs,
+				     unsigned int num_configs)
+{
+	struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	u8 bit = RZT2H_PIN_ID_TO_PIN(_pin);
+	unsigned int i;
+	int ret;
+
+	ret = rzt2h_validate_pin(pctrl, _pin);
+	if (ret)
+		return ret;
+
+	/* Adjust bit for upper half of port */
+	if (bit >= 4)
+		bit -= 4;
+
+	for (i = 0; i < num_configs; i++) {
+		u32 arg = pinconf_to_config_argument(_configs[i]);
+		u32 param = pinconf_to_config_param(_configs[i]);
+		u32 mask, val;
+
+		switch (param) {
+		case PIN_CONFIG_SLEW_RATE:
+			mask = SR_MASK << DRCTL_SR_SHIFT(bit);
+			val = (!!arg) << DRCTL_SR_SHIFT(bit);
+			break;
+
+		case PIN_CONFIG_BIAS_DISABLE:
+		case PIN_CONFIG_BIAS_PULL_UP:
+		case PIN_CONFIG_BIAS_PULL_DOWN: {
+			u32 bias = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
+				(param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2;
+
+			mask = PUPD_MASK << DRCTL_PUPD_SHIFT(bit);
+			val = bias << DRCTL_PUPD_SHIFT(bit);
+			break;
+		}
+
+		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+			mask = SCHMITT_MASK << DRCTL_SCHMITT_SHIFT(bit);
+			val = (!!arg) << DRCTL_SCHMITT_SHIFT(bit);
+			break;
+
+		case RENESAS_RZT2H_PIN_CONFIG_DRIVE_STRENGTH:
+			if (arg > IOLH_MASK)
+				return -EINVAL;
+
+			mask = IOLH_MASK << DRCTL_IOLH_SHIFT(bit);
+			val = arg << DRCTL_IOLH_SHIFT(bit);
+			break;
+
+		default:
+			return -EOPNOTSUPP;
+		}
+
+		rzt2h_drctl_rmw(pctrl, _pin, mask, val);
+	}
+
+	return 0;
+}
+
+static int rzt2h_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
+					   unsigned int group,
+					   unsigned long *configs,
+					   unsigned int num_configs)
+{
+	const unsigned int *pins;
+	unsigned int i, npins;
+	int ret;
+
+	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < npins; i++) {
+		ret = rzt2h_pinctrl_pinconf_set(pctldev, pins[i], configs,
+						num_configs);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+};
+
+static int rzt2h_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
+					   unsigned int group,
+					   unsigned long *config)
+{
+	const unsigned int *pins;
+	unsigned int i, npins, prev_config = 0;
+	int ret;
+
+	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < npins; i++) {
+		ret = rzt2h_pinctrl_pinconf_get(pctldev, pins[i], config);
+		if (ret)
+			return ret;
+
+		/* Check config matching between to pin  */
+		if (i && prev_config != *config)
+			return -EOPNOTSUPP;
+
+		prev_config = *config;
+	}
+
+	return 0;
+};
+
 static const struct pinctrl_ops rzt2h_pinctrl_pctlops = {
 	.get_groups_count = pinctrl_generic_get_group_count,
 	.get_group_name = pinctrl_generic_get_group_name,
@@ -441,6 +656,15 @@ static const struct pinmux_ops rzt2h_pinctrl_pmxops = {
 	.strict = true,
 };
 
+static const struct pinconf_ops rzt2h_pinctrl_confops = {
+	.is_generic = true,
+	.pin_config_get = rzt2h_pinctrl_pinconf_get,
+	.pin_config_set = rzt2h_pinctrl_pinconf_set,
+	.pin_config_group_set = rzt2h_pinctrl_pinconf_group_set,
+	.pin_config_group_get = rzt2h_pinctrl_pinconf_group_get,
+	.pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
 static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
 {
 	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
@@ -674,7 +898,13 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl)
 	desc->npins = pctrl->data->n_port_pins;
 	desc->pctlops = &rzt2h_pinctrl_pctlops;
 	desc->pmxops = &rzt2h_pinctrl_pmxops;
+	pctrl->desc.confops = &rzt2h_pinctrl_confops;
 	desc->owner = THIS_MODULE;
+	pctrl->desc.num_custom_params = ARRAY_SIZE(renesas_rzt2h_custom_bindings);
+	pctrl->desc.custom_params = renesas_rzt2h_custom_bindings;
+#ifdef CONFIG_DEBUG_FS
+	pctrl->desc.custom_conf_items = renesas_rzt2h_conf_items;
+#endif
 
 	pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);
 	if (!pins)
-- 
2.43.0

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3091 bytes --]

On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document the pin configuration properties supported by the RZ/T2H pinctrl
> driver. The RZ/T2H SoC supports configuring various electrical properties
> through the DRCTLm (I/O Buffer Function Switching) registers.
> 
> Add documentation for the following standard properties:
> - bias-disable, bias-pull-up, bias-pull-down: Control internal
>   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
>   input
> - slew-rate: Control output slew rate (2 options: slow/fast)
> 
> Add documentation for the custom property:
> - renesas,drive-strength: Control output drive strength using discrete
>   levels (0-3) representing low, medium, high, and ultra high strength.
>   This custom property is needed because the hardware uses fixed discrete
>   levels rather than configurable milliamp values.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> index 36d665971484..9085d5cfb1c8 100644
> --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> @@ -72,6 +72,19 @@ definitions:
>        input: true
>        input-enable: true
>        output-enable: true
> +      bias-disable: true
> +      bias-pull-down: true
> +      bias-pull-up: true
> +      input-schmitt-enable: true
> +      input-schmitt-disable: true
> +      slew-rate:
> +        enum: [0, 1]

What are the meanings of "0" and "1" for slew rate? Why isn't this given
as the actual rates? The docs surely give more detail than just "slow"
and "fast".

> +      renesas,drive-strength:
> +        description:
> +          Drive strength configuration value. Valid values are 0 to 3, representing
> +          increasing drive strength from low, medium, high and ultra high.

I see what you wrote in the commit message, but I don't really get why
you need a custom property. I would imagine most devices only have some
some small set of "fixed discrete levels", yet manage with milli- or
micro-amps fine. Converting from mA to register values in a driver is
not difficult, and I figure the documentation for the device probably
doesn't just give vague strengths like "medium" or "ultra high", but
probably provides currents?

I dunno, I am just confused by the need to shove register values into
these properties, rather than using the actual units.

> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        enum: [0, 1, 2, 3]
>      oneOf:
>        - required: [pinmux]
>        - required: [pins]
> -- 
> 2.43.0
> 

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Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Lad, Prabhakar]

Hi Conor,

Thank you for the review.

On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > driver. The RZ/T2H SoC supports configuring various electrical properties
> > through the DRCTLm (I/O Buffer Function Switching) registers.
> >
> > Add documentation for the following standard properties:
> > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> >   input
> > - slew-rate: Control output slew rate (2 options: slow/fast)
> >
> > Add documentation for the custom property:
> > - renesas,drive-strength: Control output drive strength using discrete
> >   levels (0-3) representing low, medium, high, and ultra high strength.
> >   This custom property is needed because the hardware uses fixed discrete
> >   levels rather than configurable milliamp values.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > index 36d665971484..9085d5cfb1c8 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > @@ -72,6 +72,19 @@ definitions:
> >        input: true
> >        input-enable: true
> >        output-enable: true
> > +      bias-disable: true
> > +      bias-pull-down: true
> > +      bias-pull-up: true
> > +      input-schmitt-enable: true
> > +      input-schmitt-disable: true
> > +      slew-rate:
> > +        enum: [0, 1]
>
> What are the meanings of "0" and "1" for slew rate? Why isn't this given
I'll add a description for it (0 = slow, 1 = fast) and the same values
are programmed in the register to configure the slew rate.

> as the actual rates? The docs surely give more detail than just "slow"
> and "fast".
You mean to represent slew-rate in some sort of a unit?

>
> > +      renesas,drive-strength:
> > +        description:
> > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > +          increasing drive strength from low, medium, high and ultra high.
>
> I see what you wrote in the commit message, but I don't really get why
> you need a custom property. I would imagine most devices only have some
> some small set of "fixed discrete levels", yet manage with milli- or
> micro-amps fine. Converting from mA to register values in a driver is
> not difficult, and I figure the documentation for the device probably
> doesn't just give vague strengths like "medium" or "ultra high", but
> probably provides currents?
>
> I dunno, I am just confused by the need to shove register values into
> these properties, rather than using the actual units.
>
I'm checking this with the HW team. I'll get back on this once I have
some feedback.

Cheers,
Prabhakar

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3778 bytes --]

On Fri, Oct 17, 2025 at 04:33:56PM +0100, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Thank you for the review.
> 
> On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > > driver. The RZ/T2H SoC supports configuring various electrical properties
> > > through the DRCTLm (I/O Buffer Function Switching) registers.
> > >
> > > Add documentation for the following standard properties:
> > > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> > >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> > >   input
> > > - slew-rate: Control output slew rate (2 options: slow/fast)
> > >
> > > Add documentation for the custom property:
> > > - renesas,drive-strength: Control output drive strength using discrete
> > >   levels (0-3) representing low, medium, high, and ultra high strength.
> > >   This custom property is needed because the hardware uses fixed discrete
> > >   levels rather than configurable milliamp values.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > index 36d665971484..9085d5cfb1c8 100644
> > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > @@ -72,6 +72,19 @@ definitions:
> > >        input: true
> > >        input-enable: true
> > >        output-enable: true
> > > +      bias-disable: true
> > > +      bias-pull-down: true
> > > +      bias-pull-up: true
> > > +      input-schmitt-enable: true
> > > +      input-schmitt-disable: true
> > > +      slew-rate:
> > > +        enum: [0, 1]
> >
> > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> I'll add a description for it (0 = slow, 1 = fast) and the same values
> are programmed in the register to configure the slew rate.
> 
> > as the actual rates? The docs surely give more detail than just "slow"
> > and "fast".
> You mean to represent slew-rate in some sort of a unit?

Usually slew-rate is measured in a unit derived from volts per second.
What rates do "slow" and "fast" actually represent?

> > > +      renesas,drive-strength:
> > > +        description:
> > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > +          increasing drive strength from low, medium, high and ultra high.
> >
> > I see what you wrote in the commit message, but I don't really get why
> > you need a custom property. I would imagine most devices only have some
> > some small set of "fixed discrete levels", yet manage with milli- or
> > micro-amps fine. Converting from mA to register values in a driver is
> > not difficult, and I figure the documentation for the device probably
> > doesn't just give vague strengths like "medium" or "ultra high", but
> > probably provides currents?
> >
> > I dunno, I am just confused by the need to shove register values into
> > these properties, rather than using the actual units.
> >
> I'm checking this with the HW team. I'll get back on this once I have
> some feedback.
> 
> Cheers,
> Prabhakar

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Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Linus Walleij]

On Tue, Oct 14, 2025 at 9:11 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document the pin configuration properties supported by the RZ/T2H pinctrl
> driver. The RZ/T2H SoC supports configuring various electrical properties
> through the DRCTLm (I/O Buffer Function Switching) registers.

I was going to provide some comments but Conor had already given
exactly the same comments that I would add myself, so looking
forward to the next version.

Yours,
Linus Walleij

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Lad, Prabhakar]

Hi Conor,

Sorry for the delayed response. Ive got feedback from the HW team.

On Fri, Oct 17, 2025 at 4:33 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Conor,
>
> Thank you for the review.
>
> On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > > driver. The RZ/T2H SoC supports configuring various electrical properties
> > > through the DRCTLm (I/O Buffer Function Switching) registers.
> > >
> > > Add documentation for the following standard properties:
> > > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> > >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> > >   input
> > > - slew-rate: Control output slew rate (2 options: slow/fast)
> > >
> > > Add documentation for the custom property:
> > > - renesas,drive-strength: Control output drive strength using discrete
> > >   levels (0-3) representing low, medium, high, and ultra high strength.
> > >   This custom property is needed because the hardware uses fixed discrete
> > >   levels rather than configurable milliamp values.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > index 36d665971484..9085d5cfb1c8 100644
> > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > @@ -72,6 +72,19 @@ definitions:
> > >        input: true
> > >        input-enable: true
> > >        output-enable: true
> > > +      bias-disable: true
> > > +      bias-pull-down: true
> > > +      bias-pull-up: true
> > > +      input-schmitt-enable: true
> > > +      input-schmitt-disable: true
> > > +      slew-rate:
> > > +        enum: [0, 1]
> >
> > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> I'll add a description for it (0 = slow, 1 = fast) and the same values
> are programmed in the register to configure the slew rate.
>
> > as the actual rates? The docs surely give more detail than just "slow"
> > and "fast".
> You mean to represent slew-rate in some sort of a unit?
>
Based on the comments from the HW team, there is no numerical
definition to represent slow/fast It only defines a relative
relationship.
> >
> > > +      renesas,drive-strength:
> > > +        description:
> > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > +          increasing drive strength from low, medium, high and ultra high.
> >
> > I see what you wrote in the commit message, but I don't really get why
> > you need a custom property. I would imagine most devices only have some
> > some small set of "fixed discrete levels", yet manage with milli- or
> > micro-amps fine. Converting from mA to register values in a driver is
> > not difficult, and I figure the documentation for the device probably
> > doesn't just give vague strengths like "medium" or "ultra high", but
> > probably provides currents?
> >
> > I dunno, I am just confused by the need to shove register values into
> > these properties, rather than using the actual units.
> >
> I'm checking this with the HW team. I'll get back on this once I have
> some feedback.
>
The current value is determined by the load on the external circuit
and is not affected by the choice of drive strength. For example, if a
3.3V signal line (H = 3.3V, L = 0V) has a 3.3kΩ load, the resulting
current will be 1mA, regardless of whether you select Low, Mid, High,
or Ultra High drive strength. What changes with Low/Mid/High/Ultra
High is the “slew rate” of the transitions (H --> L and L --> H), not
the current itself.

Please share your thoughts on how to implement these properties.

Cheers,
Prabhakar

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Conor Dooley]

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On Mon, Dec 08, 2025 at 10:36:04AM +0000, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Sorry for the delayed response. Ive got feedback from the HW team.
> 
> On Fri, Oct 17, 2025 at 4:33 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Conor,
> >
> > Thank you for the review.
> >
> > On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > > > driver. The RZ/T2H SoC supports configuring various electrical properties
> > > > through the DRCTLm (I/O Buffer Function Switching) registers.
> > > >
> > > > Add documentation for the following standard properties:
> > > > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> > > >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > > > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> > > >   input
> > > > - slew-rate: Control output slew rate (2 options: slow/fast)
> > > >
> > > > Add documentation for the custom property:
> > > > - renesas,drive-strength: Control output drive strength using discrete
> > > >   levels (0-3) representing low, medium, high, and ultra high strength.
> > > >   This custom property is needed because the hardware uses fixed discrete
> > > >   levels rather than configurable milliamp values.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> > > >  1 file changed, 13 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > index 36d665971484..9085d5cfb1c8 100644
> > > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > @@ -72,6 +72,19 @@ definitions:
> > > >        input: true
> > > >        input-enable: true
> > > >        output-enable: true
> > > > +      bias-disable: true
> > > > +      bias-pull-down: true
> > > > +      bias-pull-up: true
> > > > +      input-schmitt-enable: true
> > > > +      input-schmitt-disable: true
> > > > +      slew-rate:
> > > > +        enum: [0, 1]
> > >
> > > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> > I'll add a description for it (0 = slow, 1 = fast) and the same values
> > are programmed in the register to configure the slew rate.
> >
> > > as the actual rates? The docs surely give more detail than just "slow"
> > > and "fast".
> > You mean to represent slew-rate in some sort of a unit?
> >
> Based on the comments from the HW team, there is no numerical
> definition to represent slow/fast It only defines a relative
> relationship.
> > >
> > > > +      renesas,drive-strength:
> > > > +        description:
> > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > +          increasing drive strength from low, medium, high and ultra high.
> > >
> > > I see what you wrote in the commit message, but I don't really get why
> > > you need a custom property. I would imagine most devices only have some
> > > some small set of "fixed discrete levels", yet manage with milli- or
> > > micro-amps fine. Converting from mA to register values in a driver is
> > > not difficult, and I figure the documentation for the device probably
> > > doesn't just give vague strengths like "medium" or "ultra high", but
> > > probably provides currents?
> > >
> > > I dunno, I am just confused by the need to shove register values into
> > > these properties, rather than using the actual units.
> > >
> > I'm checking this with the HW team. I'll get back on this once I have
> > some feedback.
> >
> The current value is determined by the load on the external circuit
> and is not affected by the choice of drive strength. For example, if a
> 3.3V signal line (H = 3.3V, L = 0V) has a 3.3kΩ load, the resulting
> current will be 1mA, regardless of whether you select Low, Mid, High,
> or Ultra High drive strength. What changes with Low/Mid/High/Ultra
> High is the “slew rate” of the transitions (H --> L and L --> H), not
> the current itself.
> 
> Please share your thoughts on how to implement these properties.

ngl, sounds like both of these properties should be strings, but for the
fact that slew-rate is open ended and I am pretty sure used like you are
using it elsewhere.
The second property, I'm not sure what you're trying to say with your
example. Ignoring the specifics of your platform, and using the normal
drive-strength property, I wouldn't expect that, if a given drive strength
can provide 1 mA, that increasing the drive strength would increase the
current. It would be impossible for it to do so!
Remember, drive strength is the current that can be delivered through a
pin, not how much it is delivering at a given point in time.
I would also expect that increasing the drive strength (still using the
regular definition/property) would improve the rate of transition between
states, in addition to increasing the maximum drive, although not the
primary goal.

What I find weird about your explanation is that, taken at face value,
where this vendor specific property has no effect on steady-state drive
strength and only on slew rate, you have two different slew rate
controls. The regular slew-rate with 2 options and this one with 4.
That, combined with the example that doesn't make sense, casts doubt
over the explanation you're providing for what this actually is
controlling. If this truly has no impact on steady-state drive strength,
how do these two slew-rate controls actually interact? 

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Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Linus Walleij]

Hi Lad,

thanks for your patch!

On Mon, Dec 8, 2025 at 7:01 PM Conor Dooley <conor@kernel.org> wrote:
> On Mon, Dec 08, 2025 at 10:36:04AM +0000, Lad, Prabhakar wrote:

> > > > > +      slew-rate:
> > > > > +        enum: [0, 1]
> > > >
> > > > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> > > I'll add a description for it (0 = slow, 1 = fast) and the same values
> > > are programmed in the register to configure the slew rate.
> > >
> > > > as the actual rates? The docs surely give more detail than just "slow"
> > > > and "fast".
> > > You mean to represent slew-rate in some sort of a unit?
> > >
> > Based on the comments from the HW team, there is no numerical
> > definition to represent slow/fast It only defines a relative
> > relationship.

Then describe relative to what, so we can understand when to use
which setting?

> > The current value is determined by the load on the external circuit
> > and is not affected by the choice of drive strength.
(...)
> Remember, drive strength is the current that can be delivered through a
> pin, not how much it is delivering at a given point in time.

This seems to be the core of the misunderstanding here.

The setting defines the cap. How much current *can* be delivered.

If the pin controller had a fuse that would bust if we delivered too
much current, this would be the grading of that fuse.

It's the current where the driver stage(s) stop pushing in more
electrons, it's a very real thing and does not depend on what the
circuit look like.

Pins usually have protected driver stages, so connecting an
amperemeter directly to ground and driving the line high would
actually give this value.

Yours,
Linus Walleij

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Lad, Prabhakar]

Hi Linus,

Thank you for the review.

On Thu, Dec 11, 2025 at 12:00 AM Linus Walleij <linusw@kernel.org> wrote:
>
> Hi Lad,
>
> thanks for your patch!
>
> On Mon, Dec 8, 2025 at 7:01 PM Conor Dooley <conor@kernel.org> wrote:
> > On Mon, Dec 08, 2025 at 10:36:04AM +0000, Lad, Prabhakar wrote:
>
> > > > > > +      slew-rate:
> > > > > > +        enum: [0, 1]
> > > > >
> > > > > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> > > > I'll add a description for it (0 = slow, 1 = fast) and the same values
> > > > are programmed in the register to configure the slew rate.
> > > >
> > > > > as the actual rates? The docs surely give more detail than just "slow"
> > > > > and "fast".
> > > > You mean to represent slew-rate in some sort of a unit?
> > > >
> > > Based on the comments from the HW team, there is no numerical
> > > definition to represent slow/fast It only defines a relative
> > > relationship.
>
> Then describe relative to what, so we can understand when to use
> which setting?
>
I have made a query regarding this to the HW team. I'll respond as
soon as I get any feedback.

> > > The current value is determined by the load on the external circuit
> > > and is not affected by the choice of drive strength.
> (...)
> > Remember, drive strength is the current that can be delivered through a
> > pin, not how much it is delivering at a given point in time.
>
> This seems to be the core of the misunderstanding here.
>
> The setting defines the cap. How much current *can* be delivered.
>
> If the pin controller had a fuse that would bust if we delivered too
> much current, this would be the grading of that fuse.
>
> It's the current where the driver stage(s) stop pushing in more
> electrons, it's a very real thing and does not depend on what the
> circuit look like.
>
> Pins usually have protected driver stages, so connecting an
> amperemeter directly to ground and driving the line high would
> actually give this value.
>
Agreed.

Cheers,
Prabhakar

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Lad, Prabhakar]

Hi All,

Sorry for the late reply.

On Mon, Dec 8, 2025 at 6:01 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, Dec 08, 2025 at 10:36:04AM +0000, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > Sorry for the delayed response. Ive got feedback from the HW team.
> >
> > On Fri, Oct 17, 2025 at 4:33 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > >
> > > Hi Conor,
> > >
> > > Thank you for the review.
> > >
> > > On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > > > > driver. The RZ/T2H SoC supports configuring various electrical properties
> > > > > through the DRCTLm (I/O Buffer Function Switching) registers.
> > > > >
> > > > > Add documentation for the following standard properties:
> > > > > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> > > > >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > > > > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> > > > >   input
> > > > > - slew-rate: Control output slew rate (2 options: slow/fast)
> > > > >
> > > > > Add documentation for the custom property:
> > > > > - renesas,drive-strength: Control output drive strength using discrete
> > > > >   levels (0-3) representing low, medium, high, and ultra high strength.
> > > > >   This custom property is needed because the hardware uses fixed discrete
> > > > >   levels rather than configurable milliamp values.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> > > > >  1 file changed, 13 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > index 36d665971484..9085d5cfb1c8 100644
> > > > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > @@ -72,6 +72,19 @@ definitions:
> > > > >        input: true
> > > > >        input-enable: true
> > > > >        output-enable: true
> > > > > +      bias-disable: true
> > > > > +      bias-pull-down: true
> > > > > +      bias-pull-up: true
> > > > > +      input-schmitt-enable: true
> > > > > +      input-schmitt-disable: true
> > > > > +      slew-rate:
> > > > > +        enum: [0, 1]
> > > >
> > > > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> > > I'll add a description for it (0 = slow, 1 = fast) and the same values
> > > are programmed in the register to configure the slew rate.
> > >
> > > > as the actual rates? The docs surely give more detail than just "slow"
> > > > and "fast".
> > > You mean to represent slew-rate in some sort of a unit?
> > >
> > Based on the comments from the HW team, there is no numerical
> > definition to represent slow/fast It only defines a relative
> > relationship.
> > > >
> > > > > +      renesas,drive-strength:
> > > > > +        description:
> > > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > > +          increasing drive strength from low, medium, high and ultra high.
> > > >
I got the feedback from the HW team "The RZ/T2H drive strength
(driving ability) is expressed using abstract levels such as Low,
Middle, and High. These values do not correspond directly to specific
mA units. To determine how much current the pin can actually drive,
the engineer must refer to the electrical characteristics table.
Therefore, the drive strength in RZ/T2H is a parameter that switches
the internal output transistor mode rather than directly representing
a physical drive current.
Consequently, expressing RZ/T2H drive strength in milli- or
micro-amps, as suggested by the reviewer, is inappropriate. To
accurately reflect the SoC's hardware specification, introducing a
custom property is essential."

To elaborate more on this [0] has the tables which are extracted from
the HW manual [1] (which needs login). For example, considering SDHI
referring to table 58.39 in [0] the drive strength can be calculated
for SD using  I = C × (delta V / deltaT).

For (SD) SDR104/ (eMMC)HS200 case C = 15pf, VDD1833 = 1.8 V and
rise/fall time 1ns that would result to 27.000 mA
For (SD) SDR50, SDR25, SDR12 (eMMC) High Speed SDR case C = 20pf,
VDD1833 = 1.8 V and rise/fall time 2ns that would result to 18.000 mA

As the drive strength is varying based on the speeds this cannot be
tied up to the fixed value. Hence to simplify the Table 58.11 in [0]
lists out the required drive strength and slew rate based on operating
voltage levels.

[0] https://gist.github.com/prabhakarlad/026a73c3a3922da2b88d0578db68276c
[1] https://www.renesas.com/en/document/mah/rzt2h-and-rzn2h-groups-users-manual-hardware?language=en&r=25567515

Please share your thoughts.

Cheers,
Prabhakar

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Conor Dooley]

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On Wed, Jan 14, 2026 at 08:53:12PM +0000, Lad, Prabhakar wrote:
> Hi All,
> 
> Sorry for the late reply.
> 
> On Mon, Dec 8, 2025 at 6:01 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Mon, Dec 08, 2025 at 10:36:04AM +0000, Lad, Prabhakar wrote:
> > > Hi Conor,
> > >
> > > Sorry for the delayed response. Ive got feedback from the HW team.
> > >
> > > On Fri, Oct 17, 2025 at 4:33 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > Hi Conor,
> > > >
> > > > Thank you for the review.
> > > >
> > > > On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@kernel.org> wrote:
> > > > >
> > > > > On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > > > > > driver. The RZ/T2H SoC supports configuring various electrical properties
> > > > > > through the DRCTLm (I/O Buffer Function Switching) registers.
> > > > > >
> > > > > > Add documentation for the following standard properties:
> > > > > > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> > > > > >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > > > > > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> > > > > >   input
> > > > > > - slew-rate: Control output slew rate (2 options: slow/fast)
> > > > > >
> > > > > > Add documentation for the custom property:
> > > > > > - renesas,drive-strength: Control output drive strength using discrete
> > > > > >   levels (0-3) representing low, medium, high, and ultra high strength.
> > > > > >   This custom property is needed because the hardware uses fixed discrete
> > > > > >   levels rather than configurable milliamp values.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > ---
> > > > > >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> > > > > >  1 file changed, 13 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > > index 36d665971484..9085d5cfb1c8 100644
> > > > > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > > @@ -72,6 +72,19 @@ definitions:
> > > > > >        input: true
> > > > > >        input-enable: true
> > > > > >        output-enable: true
> > > > > > +      bias-disable: true
> > > > > > +      bias-pull-down: true
> > > > > > +      bias-pull-up: true
> > > > > > +      input-schmitt-enable: true
> > > > > > +      input-schmitt-disable: true
> > > > > > +      slew-rate:
> > > > > > +        enum: [0, 1]
> > > > >
> > > > > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> > > > I'll add a description for it (0 = slow, 1 = fast) and the same values
> > > > are programmed in the register to configure the slew rate.
> > > >
> > > > > as the actual rates? The docs surely give more detail than just "slow"
> > > > > and "fast".
> > > > You mean to represent slew-rate in some sort of a unit?
> > > >
> > > Based on the comments from the HW team, there is no numerical
> > > definition to represent slow/fast It only defines a relative
> > > relationship.
> > > > >
> > > > > > +      renesas,drive-strength:
> > > > > > +        description:
> > > > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > > > +          increasing drive strength from low, medium, high and ultra high.
> > > > >
> I got the feedback from the HW team "The RZ/T2H drive strength
> (driving ability) is expressed using abstract levels such as Low,
> Middle, and High. These values do not correspond directly to specific
> mA units. To determine how much current the pin can actually drive,
> the engineer must refer to the electrical characteristics table.
> Therefore, the drive strength in RZ/T2H is a parameter that switches
> the internal output transistor mode rather than directly representing
> a physical drive current.
> Consequently, expressing RZ/T2H drive strength in milli- or
> micro-amps, as suggested by the reviewer, is inappropriate. To
> accurately reflect the SoC's hardware specification, introducing a
> custom property is essential."

I feel kinda stupid reading the extracted portions of the document, is
it not just telling us what the drive strengths are in the "Conditions"
cell of the output voltage rows?
They don't directly correspond to current values, since it varies based
on the type of buffer and the voltage level. Is that what your hardware
guys are trying to say? That there's not a 1:1 fixed mapping because the
meanings of "low" etc vary based on voltage and buffer?

If that's the case, the voltage is discernible from "power-source", can
the buffer type be determined from the pin number? Or maybe both can be
determined from the pin number?

> 
> To elaborate more on this [0] has the tables which are extracted from
> the HW manual [1] (which needs login). For example, considering SDHI
> referring to table 58.39 in [0] the drive strength can be calculated
> for SD using  I = C × (delta V / deltaT).
> 
> For (SD) SDR104/ (eMMC)HS200 case C = 15pf, VDD1833 = 1.8 V and
> rise/fall time 1ns that would result to 27.000 mA
> For (SD) SDR50, SDR25, SDR12 (eMMC) High Speed SDR case C = 20pf,
> VDD1833 = 1.8 V and rise/fall time 2ns that would result to 18.000 mA
> 
> As the drive strength is varying based on the speeds this cannot be
> tied up to the fixed value. Hence to simplify the Table 58.11 in [0]
> lists out the required drive strength and slew rate based on operating
> voltage levels.
> 
> [0] https://gist.github.com/prabhakarlad/026a73c3a3922da2b88d0578db68276c
> [1] https://www.renesas.com/en/document/mah/rzt2h-and-rzn2h-groups-users-manual-hardware?language=en&r=25567515
> 
> Please share your thoughts.
> 
> Cheers,
> Prabhakar

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Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Krzysztof Kozlowski]

On 14/01/2026 21:53, Lad, Prabhakar wrote:
>>>>> What are the meanings of "0" and "1" for slew rate? Why isn't this given
>>>> I'll add a description for it (0 = slow, 1 = fast) and the same values
>>>> are programmed in the register to configure the slew rate.
>>>>
>>>>> as the actual rates? The docs surely give more detail than just "slow"
>>>>> and "fast".
>>>> You mean to represent slew-rate in some sort of a unit?
>>>>
>>> Based on the comments from the HW team, there is no numerical
>>> definition to represent slow/fast It only defines a relative
>>> relationship.
>>>>>
>>>>>> +      renesas,drive-strength:
>>>>>> +        description:
>>>>>> +          Drive strength configuration value. Valid values are 0 to 3, representing
>>>>>> +          increasing drive strength from low, medium, high and ultra high.
>>>>>
> I got the feedback from the HW team "The RZ/T2H drive strength
> (driving ability) is expressed using abstract levels such as Low,
> Middle, and High. These values do not correspond directly to specific

Hold my beer and let me design PCB... I will use high voltage power
supply, then small resistor and small capacitor. Ah, and that regulator
here should operate on medium/middle voltage. Looks about right, all
ready to send to fab!

> mA units. To determine how much current the pin can actually drive,
> the engineer must refer to the electrical characteristics table.
> Therefore, the drive strength in RZ/T2H is a parameter that switches
> the internal output transistor mode rather than directly representing
> a physical drive current.
> Consequently, expressing RZ/T2H drive strength in milli- or
> micro-amps, as suggested by the reviewer, is inappropriate. To
> accurately reflect the SoC's hardware specification, introducing a
> custom property is essential."

So the hardware team tells you how you should model DT - "introducing a
custom property is essential".

That's pretty bold statement and very poor language construct. It is not
hardware team which decides how DT should be written.


Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Linus Walleij]

Hi Lad,

I think this back-and-forth must be a bit stressful. Sorry about that.

On Wed, Jan 14, 2026 at 9:53 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:

> > > > > > +      renesas,drive-strength:
> > > > > > +        description:
> > > > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > > > +          increasing drive strength from low, medium, high and ultra high.
> > > > >

> I got the feedback from the HW team "The RZ/T2H drive strength
> (driving ability) is expressed using abstract levels such as Low,
> Middle, and High. These values do not correspond directly to specific
> mA units.

But they do correspond to *something* electrical inside the
silicon do they not? Then what is that?

I think it is just 1, 2, 3 or 4 driver stages.

> To determine how much current the pin can actually drive,
> the engineer must refer to the electrical characteristics table.
> Therefore, the drive strength in RZ/T2H is a parameter that switches
> the internal output transistor mode rather than directly representing
> a physical drive current.
>
> Consequently, expressing RZ/T2H drive strength in milli- or
> micro-amps, as suggested by the reviewer, is inappropriate. To
> accurately reflect the SoC's hardware specification, introducing a
> custom property is essential."

This is past my point. What is the maximum current dissapation?

I am asking for the current flowing through the pin if it connected
to ground and 1 second after the driver is turned on, or however
long time it takes for any dynamic transients to die out.

> To elaborate more on this [0] has the tables which are extracted from
> the HW manual [1] (which needs login). For example, considering SDHI
> referring to table 58.39 in [0] the drive strength can be calculated
> for SD using  I = C × (delta V / deltaT).

This is so clearly about dynamic currents, I am asking for
*static* *maximum* for each setting. In SI unit, milliamperes.

The document says:

  drive-strength-microamp:
    description: sink or source at most X uA

So *at most*.
And low, middle, high isn't any SI unit.

If you *really* want to make this complicated and related to
an equation using capacitance, voltage and time, then you are
perhaps looking for the slew-rate property:

  slew-rate:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: set the slew rate

This we haven't defined, because it has exactly the dynamic
properties you are talking about. It can be low/medium/high
and depend on the load. It reflects something like
V/s (voltage change per time unit) in the end.

Yours,
Linus Walleij

Re: [PATCH 2/2] pinctrl: renesas: rzt2h: Add pin configuration support

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 14 Oct 2025 at 21:11, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H allows
> configuring pin properties through the DRCTLm (I/O Buffer Function
> Switching) registers, including:
> - Drive strength (low/middle/high/ultra high)
> - Pull-up/pull-down/no-bias configuration (3 options: no pull, pull-up,
>   pull-down)
> - Schmitt trigger control (enable/disable)
> - Slew rate control (2 options: slow/fast)
>
> The drive strength configuration uses four discrete levels (low, middle,
> high, ultra high) rather than the standard milliamp values. To properly
> represent this hardware behavior, implement a custom device-tree binding
> parameter "renesas,drive-strength" that accepts values 0-3 corresponding
> to these discrete levels.
>
> The DRCTLm registers are accessed in 32-bit mode, with each port split
> into two halves (bits 0-3 and bits 4-7) requiring separate register
> offsets.
>
> Implement pinconf_ops to support:
> - Getting/setting individual pin configurations
> - Getting/setting pin group configurations
> - Standard properties: bias-disable, bias-pull-up, bias-pull-down,
>   input-schmitt-enable, slew-rate
> - Custom property: renesas,drive-strength
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Just a minor drive-by comment for a patch that is still WIP...

> --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c

> +static void rzt2h_drctl_rmw(struct rzt2h_pinctrl *pctrl, unsigned int pin,
> +                           u32 mask, u32 val)
> +{
> +       u32 port = RZT2H_PIN_ID_TO_PORT(pin);
> +       u8 bit = RZT2H_PIN_ID_TO_PIN(pin);
> +       u32 offset = DRCTL(port);
> +       unsigned long flags;
> +       u32 drctl;
> +
> +       /* Access DRCTLm register in 32-bit mode */
> +       if (bit >= 4)
> +               offset += 4;
> +
> +       spin_lock_irqsave(&pctrl->lock, flags);

Please use "guard(spinlock_irqsave)(&pctrl->lock);" instead, to match
the style of the rest of the file.

Note that that will become "raw_spinlock_irqsave" soon, due to
"[PATCH v2] pinctrl: renesas: rzt2h: fix invalid wait context".

> +       drctl = rzt2h_pinctrl_readl(pctrl, port, offset) & ~mask;
> +       rzt2h_pinctrl_writel(pctrl, port, drctl | val, offset);
> +       spin_unlock_irqrestore(&pctrl->lock, flags);
> +}

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] pinctrl: renesas: rzt2h: Add pin configuration support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Mar 3, 2026 at 1:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 14 Oct 2025 at 21:11, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H allows
> > configuring pin properties through the DRCTLm (I/O Buffer Function
> > Switching) registers, including:
> > - Drive strength (low/middle/high/ultra high)
> > - Pull-up/pull-down/no-bias configuration (3 options: no pull, pull-up,
> >   pull-down)
> > - Schmitt trigger control (enable/disable)
> > - Slew rate control (2 options: slow/fast)
> >
> > The drive strength configuration uses four discrete levels (low, middle,
> > high, ultra high) rather than the standard milliamp values. To properly
> > represent this hardware behavior, implement a custom device-tree binding
> > parameter "renesas,drive-strength" that accepts values 0-3 corresponding
> > to these discrete levels.
> >
> > The DRCTLm registers are accessed in 32-bit mode, with each port split
> > into two halves (bits 0-3 and bits 4-7) requiring separate register
> > offsets.
> >
> > Implement pinconf_ops to support:
> > - Getting/setting individual pin configurations
> > - Getting/setting pin group configurations
> > - Standard properties: bias-disable, bias-pull-up, bias-pull-down,
> >   input-schmitt-enable, slew-rate
> > - Custom property: renesas,drive-strength
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Just a minor drive-by comment for a patch that is still WIP...
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
>
> > +static void rzt2h_drctl_rmw(struct rzt2h_pinctrl *pctrl, unsigned int pin,
> > +                           u32 mask, u32 val)
> > +{
> > +       u32 port = RZT2H_PIN_ID_TO_PORT(pin);
> > +       u8 bit = RZT2H_PIN_ID_TO_PIN(pin);
> > +       u32 offset = DRCTL(port);
> > +       unsigned long flags;
> > +       u32 drctl;
> > +
> > +       /* Access DRCTLm register in 32-bit mode */
> > +       if (bit >= 4)
> > +               offset += 4;
> > +
> > +       spin_lock_irqsave(&pctrl->lock, flags);
>
> Please use "guard(spinlock_irqsave)(&pctrl->lock);" instead, to match
> the style of the rest of the file.
>
Agreed.

> Note that that will become "raw_spinlock_irqsave" soon, due to
> "[PATCH v2] pinctrl: renesas: rzt2h: fix invalid wait context".
>
Thanks for the heads up.

Cheers,
Prabhakar

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Lad, Prabhakar]

Hi All,

On Mon, Jan 19, 2026 at 12:10 AM Linus Walleij <linusw@kernel.org> wrote:
>
> Hi Lad,
>
> I think this back-and-forth must be a bit stressful. Sorry about that.
>
> On Wed, Jan 14, 2026 at 9:53 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
>
> > > > > > > +      renesas,drive-strength:
> > > > > > > +        description:
> > > > > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > > > > +          increasing drive strength from low, medium, high and ultra high.
> > > > > >
>
> > I got the feedback from the HW team "The RZ/T2H drive strength
> > (driving ability) is expressed using abstract levels such as Low,
> > Middle, and High. These values do not correspond directly to specific
> > mA units.
>
> But they do correspond to *something* electrical inside the
> silicon do they not? Then what is that?
>
> I think it is just 1, 2, 3 or 4 driver stages.
>
> > To determine how much current the pin can actually drive,
> > the engineer must refer to the electrical characteristics table.
> > Therefore, the drive strength in RZ/T2H is a parameter that switches
> > the internal output transistor mode rather than directly representing
> > a physical drive current.
> >
> > Consequently, expressing RZ/T2H drive strength in milli- or
> > micro-amps, as suggested by the reviewer, is inappropriate. To
> > accurately reflect the SoC's hardware specification, introducing a
> > custom property is essential."
>
Sorry for the confusion , there was a miscommunication regarding the
specs, but it’s all been sorted out. The drive-strength settings on
this chip are 2.5/5/9/11.8 mA, I will represent them using the
drive-strength-microamp DT property and send a new version.

Cheers,
Prabhakar

Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Conor Dooley]

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On Wed, Mar 18, 2026 at 09:30:06PM +0000, Lad, Prabhakar wrote:
> Hi All,
> 
> On Mon, Jan 19, 2026 at 12:10 AM Linus Walleij <linusw@kernel.org> wrote:
> >
> > Hi Lad,
> >
> > I think this back-and-forth must be a bit stressful. Sorry about that.
> >
> > On Wed, Jan 14, 2026 at 9:53 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> >
> > > > > > > > +      renesas,drive-strength:
> > > > > > > > +        description:
> > > > > > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > > > > > +          increasing drive strength from low, medium, high and ultra high.
> > > > > > >
> >
> > > I got the feedback from the HW team "The RZ/T2H drive strength
> > > (driving ability) is expressed using abstract levels such as Low,
> > > Middle, and High. These values do not correspond directly to specific
> > > mA units.
> >
> > But they do correspond to *something* electrical inside the
> > silicon do they not? Then what is that?
> >
> > I think it is just 1, 2, 3 or 4 driver stages.
> >
> > > To determine how much current the pin can actually drive,
> > > the engineer must refer to the electrical characteristics table.
> > > Therefore, the drive strength in RZ/T2H is a parameter that switches
> > > the internal output transistor mode rather than directly representing
> > > a physical drive current.
> > >
> > > Consequently, expressing RZ/T2H drive strength in milli- or
> > > micro-amps, as suggested by the reviewer, is inappropriate. To
> > > accurately reflect the SoC's hardware specification, introducing a
> > > custom property is essential."
> >
> Sorry for the confusion , there was a miscommunication regarding the
> specs, but it’s all been sorted out. The drive-strength settings on
> this chip are 2.5/5/9/11.8 mA, I will represent them using the
> drive-strength-microamp DT property and send a new version.

neat :)

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Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties

[Linus Walleij]

On Wed, Mar 18, 2026 at 10:30 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:

> Sorry for the confusion , there was a miscommunication regarding the
> specs, but it’s all been sorted out. The drive-strength settings on
> this chip are 2.5/5/9/11.8 mA, I will represent them using the
> drive-strength-microamp DT property and send a new version.

Excellent!

Thanks for going the extra mile with the Lad, much appreciated!

Yours,
Linus Walleij