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Tue, 9 Dec 2025 08:51:50 -0800 From: To: , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [RFC v2 09/15] vfio/cxl: introduce vfio_cxl_core_{read, write}() Date: Tue, 9 Dec 2025 22:20:13 +0530 Message-ID: <20251209165019.2643142-10-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251209165019.2643142-1-mhonap@nvidia.com> References: <20251209165019.2643142-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|IA1PR12MB6306:EE_ X-MS-Office365-Filtering-Correlation-Id: 62efd164-6433-407f-3f3b-08de37435441 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?tPU5Xd8IzMSnBAtzl5xkTn61hxAEfzlHPRmPhEKvCx/NoikzBnXdTlcCN9r8?= =?us-ascii?Q?ABgmxbSyXxqe9Y6Tab/5cUzw4LFm8MasdfdvmBGrQkbfVWZd4CWRfrzXLZne?= =?us-ascii?Q?sueXIsUmWlQjbBt9/cyExMFDdQV2tG8IVT6vbL2POgetQZwn5SByqJ4O7w8y?= =?us-ascii?Q?eyQWasKpPpzKBdzRwsmkJknWGR8oCcfIYuusWVHwcl37xsA3ByHSlOeqIhKg?= =?us-ascii?Q?ruOSymlNIWYy1JZV9R8gjHdK/X3XlnxpQbMK/AE4nZdowU+FZUKwyHHHRKzZ?= =?us-ascii?Q?ffVRiVLgoaJ9yhAKP3StoXJzKPeGR1KL9nXmGLWIU/p9E11kGKZd1zMNYQVv?= =?us-ascii?Q?lPcpDZh8t/V+G2R1P9u1YwwqbH4BV+u41XtiVz/iGc8b8OHLzvc3nzNRFhqj?= =?us-ascii?Q?m0jZC4ZMnfUDNMnFVmpDLFw3LLJ7XlRpXuCC2DULfzQIvJduCor9Rq831FZc?= =?us-ascii?Q?gZNlZRHoJa8UiTN5taXaUzcIjIHPEvqvpq6ikRXyW7WLIqAFx4JtRyoVMoAb?= =?us-ascii?Q?fT7cd4Ua2v3PKdvh8ieVF7H+2RUp6Z0zvRDQc6lk0+nMoJPPUmy80lZBKA99?= =?us-ascii?Q?6HhLqBoQ+Qw4ZCCvcMnD4cd/76lG+7PMErYh0xVrZi7OxZ2jUckEYgxr3keS?= =?us-ascii?Q?AXgr1g+qstVG5u+tZy+AnpaV5GXHlgGibJDZjdxoMj826EYoc29hr0E2sbmW?= =?us-ascii?Q?pwEYbEEau6k42P418e/pQJcR6LRUWJiAVD2xK8CzlIHV13PXeYyV4pRiC3VZ?= =?us-ascii?Q?egHuZ16goQJY/CjxwZ7UukH8mH8lTG/CIiEZY0CqGVklB+a6ipkZRBMRI2gk?= =?us-ascii?Q?QA5TGbp3WQXTkJAC2qoNLOQb34w+Hv3bow2NfYxOdBIZbt1d+Ub7N467vLlb?= =?us-ascii?Q?brUeK3QbBZGnGcLiF0FyqPNwihhMhGVLIFfJwSsjpC3VHNpYaMGbdEQOyfNn?= =?us-ascii?Q?ZdKebOGlu4mfDtl9B1p2AMlZrcKWFsZUs7BM4zTox+dIOenA9QUF3B5iqGtM?= =?us-ascii?Q?cJEMPPz+a1PehWfApVlb6CvrzuRCnkwTuL93ql6B/9/rDo+AEOLoX68O+5Cz?= =?us-ascii?Q?J2dOBZGJyvI8IGecbrEvgTodhaFfp/gMigaYZ6qha9EEqaou2SBLXYWpfaAV?= =?us-ascii?Q?kiCAys18ZmCpbIf8izdjJTsRTEcNqoJoG8Vwbysg/0d4L/wXghPL912GL9e7?= =?us-ascii?Q?V6+f7mSMSSZcBb1KX67cFbbCxHmw31hJ1t9DsqtIXo09ctWrYo4Qieew/Ja8?= =?us-ascii?Q?rrHCRPqTD/aqQ0hjwEIGWBcItquGeshCFX7wJHoJ52v4TZjUvauDAmLqT/nS?= =?us-ascii?Q?pesgZvXvVTZ4xgjonZak7BqF3fWGtC9jgU12/JdyD57Azo2a6xc7EoCzxnBs?= =?us-ascii?Q?f8/JUgvG+x1q8mC9LUL2RqNeoyYnzX3Oa7ycTz8bb9J73iBd0+WKOJaOpzIN?= =?us-ascii?Q?N0+cJ+w3v7YSJR1Uc5OeMGiBJ3eK96/TjUL7fSPUW6H0jYe4TojULHlyADs9?= =?us-ascii?Q?i6+gik9y0RQftw8v1al9vgzd0Xn42NbjrutqDqcDVAzS+c18wK+8l9gzT97E?= =?us-ascii?Q?E7xpuNAcYueDIAOiag7mSUiPeT5Fh9PWQgjZuVZY?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2025 16:52:24.7805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62efd164-6433-407f-3f3b-08de37435441 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6306 From: Zhi Wang The read/write callbacks in vfio_device_ops is for accessing the device when mmap is not support. It is also used for VFIO variant driver to emulate the device registers. CXL spec illusrates the standard programming interface, part of them are MMIO registers sit in a PCI BAR. Some of them are emulated when passing the CXL type-2 device to the VM. E.g. HDM decoder registers are emulated. Introduce vfio_cxl_core_{read, write}() in the vfio-cxl-core to prepare for emulating the CXL MMIO registers in the PCI BAR. Signed-off-by: Zhi Wang Signed-off-by: Manish Honap --- drivers/vfio/pci/vfio_cxl_core.c | 20 ++++++++++++++++++++ drivers/vfio/pci/vfio_pci_core.c | 5 +++-- include/linux/vfio_pci_core.h | 6 ++++++ 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index 099d35866a39..460f1ee910af 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -378,6 +378,26 @@ void vfio_cxl_core_unregister_cxl_region(struct vfio_cxl_core_device *cxl) } EXPORT_SYMBOL_GPL(vfio_cxl_core_unregister_cxl_region); +ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, + size_t count, loff_t *ppos) +{ + struct vfio_pci_core_device *vdev = + container_of(core_vdev, struct vfio_pci_core_device, vdev); + + return vfio_pci_rw(vdev, buf, count, ppos, false); +} +EXPORT_SYMBOL_GPL(vfio_cxl_core_read); + +ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct vfio_pci_core_device *vdev = + container_of(core_vdev, struct vfio_pci_core_device, vdev); + + return vfio_pci_rw(vdev, (char __user *)buf, count, ppos, true); +} +EXPORT_SYMBOL_GPL(vfio_cxl_core_write); + MODULE_LICENSE("GPL"); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index c0695b5db66d..502880e927fc 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1520,8 +1520,8 @@ int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, } EXPORT_SYMBOL_GPL(vfio_pci_core_ioctl_feature); -static ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, - size_t count, loff_t *ppos, bool iswrite) +ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool iswrite) { unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); int ret; @@ -1566,6 +1566,7 @@ static ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, pm_runtime_put(&vdev->pdev->dev); return ret; } +EXPORT_SYMBOL_GPL(vfio_pci_rw); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 7237fcaecbb6..a6885b48f26f 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -153,6 +153,8 @@ long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd, unsigned long arg); int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, void __user *arg, size_t argsz); +ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool iswrite); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos); ssize_t vfio_pci_core_write(struct vfio_device *core_vdev, const char __user *buf, @@ -216,5 +218,9 @@ int vfio_cxl_core_create_cxl_region(struct vfio_cxl_core_device *cxl, u64 size); void vfio_cxl_core_destroy_cxl_region(struct vfio_cxl_core_device *cxl); int vfio_cxl_core_register_cxl_region(struct vfio_cxl_core_device *cxl); void vfio_cxl_core_unregister_cxl_region(struct vfio_cxl_core_device *cxl); +ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, + size_t count, loff_t *ppos); +ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *buf, + size_t count, loff_t *ppos); #endif /* VFIO_PCI_CORE_H */ -- 2.25.1