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Tue, 9 Dec 2025 08:52:20 -0800 From: To: , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [RFC v2 13/15] vfio/pci: introduce CXL device awareness Date: Tue, 9 Dec 2025 22:20:17 +0530 Message-ID: <20251209165019.2643142-14-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251209165019.2643142-1-mhonap@nvidia.com> References: <20251209165019.2643142-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|CH2PR12MB4166:EE_ X-MS-Office365-Filtering-Correlation-Id: c2c78d13-2cf5-4309-9aea-08de37436405 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?02MgoSwtP1wFlIadi7GmXhkwGuAiNUdQQ3Mn2WrTydLaGuF0d8mUAYk2W0O6?= =?us-ascii?Q?x92scuGZc2SmOQCvr5lWEUC6FYwfVwE4AZO6vpfJWokOJyx1onXBbgxqj7Sw?= =?us-ascii?Q?IVLQDC0KFgdLJ2aoN9kj10nmU8ZdpdP36frqa1piP8XcL3w7KOXtDBa/voUI?= =?us-ascii?Q?8t6ErFiglMDMz4Rs2mI+Hdacj1NWII9RljLUMnFVe6rdwEYA/+kdi3SyiOVm?= =?us-ascii?Q?OUBzKfJ0uRgdavkBhGpZiy1NaHWFYNdBY+vuidnLpjE7PIUExuFQA9/afPNe?= =?us-ascii?Q?/rI0gotuzxXzbkmq2b5JNrn0AX+/cCtmBPFM+RMr/sA9n+/AzLD1DkDmtMZ+?= =?us-ascii?Q?x0IE9oUYXgVOpKutZpe7n0r68qSmRH2Yt14dbko98M+v5TdLPgGWHHsXCsqq?= =?us-ascii?Q?QiCGaYQhlA6DK4hzNKiQCZM2I/Ei2JaxMScHMndm7zxcmBliB6xMOM3myi9d?= =?us-ascii?Q?omksgnxE/Ejy8S3HB+anDt1EFz4c9D6jVQ/Te1hc+gdViTL/qybtc//NqiUZ?= =?us-ascii?Q?07YtVKyuTi2YDfEHqtdtb9s9At8I5o30dp5kD8zv8Ndr3VLhRhhSVyU7BKB/?= =?us-ascii?Q?1nXR8FjyKL9pVp5BDi8VYY5HsSZLheV+Sa4bENtWB/+0id6EQM5oRo0lm/na?= =?us-ascii?Q?Pn2GGT6aAhG6TsTPFA2Xa3XNOAqHP7k5ywyG/OFbCxa5wyPFWlEcxPHwnxTd?= =?us-ascii?Q?L7AYOPUj2VTGXRsw2MeesJ67XjqSSSVNre+QRkHuc1xTs1s3BuftnjW4ZlBE?= =?us-ascii?Q?Bm0djXcEOOK37LZghx0AlatoGlLVf28a8bXmlaTvoGaCl7pSecpKhtbg2sh3?= =?us-ascii?Q?sU8XQC+qMwWOrYelBo986N+CBPKyj568gj4fi5txYpAe5Zp1xm2I2Ki9LgBI?= =?us-ascii?Q?8JAKrJ87iCCEL68Zn2jm0cYofNavKJOIaw+hmri45t1mKI117dh1/9wN7V8G?= =?us-ascii?Q?yCT2cU3KPdkGgMtrHQlBOHBEHqmKGvfyW8IDaIyN6Tb/3hzUCzKB5yNjBcd1?= =?us-ascii?Q?CJHq+Qg5IGExwc2S7I/WiMQW1RkXL3JhZzsdW2wJM01Aw4naLpEqFwq83m5i?= =?us-ascii?Q?Sk4vCWWVB2oL6hyRkzb2zFLPicl5rc5iMu+at6mXTUwivEGu2mwD8TigrYyI?= =?us-ascii?Q?ifrWMirxCKfMKC4omiDNldqH9eWpwUZwV8zve3AgofN5GUyt5wMGgXphZG9g?= =?us-ascii?Q?EqK5Yn8X1xWYmSl+SgxAsFCywdrOOhddkTGD5iomvbJDcdA3hwuH6rRWbpAV?= =?us-ascii?Q?z30z745zQTHkrK7ZyL/XnoBJwf7HW5RZWIUAbGVDeRI7g5lj/iGEgeQr2y/1?= =?us-ascii?Q?iucZXzowqi44EZ8WV3eT9aoNeJJakLHvlIfUsM4IhK+orltIZlkzdtnDhpTV?= =?us-ascii?Q?iJ2cUhtiXE6rqJvLe2EsVSkWxbjOKrw5enp4rBWF/3RvNXDZftGQDBhpEEp1?= =?us-ascii?Q?Gg2FURmZwrWHP4GkINKdCl8Po0QJhVOwv8hZf2Z00O9Wu1v0jQQALwMgGOH4?= =?us-ascii?Q?ZVcML/AQMtRiVjEvFYxDi1cbUUhMIBfX3q8+JZ2Lz4WV9YoX/X0riaZulooG?= =?us-ascii?Q?F0ZUqcEz6RukFczxy1zXIdSCFOQ3HA1Z8GKbJgYT?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2025 16:52:51.2078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2c78d13-2cf5-4309-9aea-08de37436405 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4166 From: Zhi Wang CXL device programming interfaces are built upon PCI interfaces. Thus the vfio-pci-core can be leveraged to handle a CXL device. However, CXL device also has difference with PCI devicce: - No INTX support, only MSI/MSIX is supported. - Reset is done via CXL reset. FLR only reset CXL.io. Introduce the CXL device awareness to the vfio-pci-core. Expose a new VFIO device flags to the userspace to identify the VFIO device is a CXL device. Disable INTX support in the vfio-pci-core. Disable FLR reset for the CXL device as the kernel CXL core hasn't support CXL reset yet. Disable mmap support on the CXL MMIO BAR in vfio-pci-core. Signed-off-by: Zhi Wang Signed-off-by: Manish Honap --- drivers/vfio/pci/vfio_cxl_core.c | 18 +++++++++++++++++ drivers/vfio/pci/vfio_pci_core.c | 33 ++++++++++++++++++++++++++++---- drivers/vfio/pci/vfio_pci_rdwr.c | 11 ++++++++--- include/linux/vfio_pci_core.h | 3 +++ include/uapi/linux/vfio.h | 10 ++++++++++ 5 files changed, 68 insertions(+), 7 deletions(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index c0bdf55997da..84e4f42d97de 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -25,6 +25,19 @@ #define DRIVER_AUTHOR "Zhi Wang " #define DRIVER_DESC "core driver for VFIO based CXL devices" +static void init_cxl_cap(struct vfio_cxl_core_device *cxl) +{ + struct vfio_pci_core_device *pci = &cxl->pci_core; + struct vfio_device_info_cap_cxl *cap = &pci->cxl_cap; + + cap->header.id = VFIO_DEVICE_INFO_CAP_CXL; + cap->header.version = 1; + cap->hdm_count = cxl->hdm_count; + cap->hdm_reg_offset = cxl->comp_reg_offset + cxl->hdm_reg_offset; + cap->hdm_reg_size = cxl->hdm_reg_size; + cap->hdm_reg_bar_index = cxl->comp_reg_bar; +} + /* Standard CXL-type 2 driver initialization sequence */ static int enable_cxl(struct vfio_cxl_core_device *cxl, u16 dvsec, struct vfio_cxl_dev_info *info) @@ -74,6 +87,8 @@ static int enable_cxl(struct vfio_cxl_core_device *cxl, u16 dvsec, if (IS_ERR(cxl_core->cxlmd)) return PTR_ERR(cxl_core->cxlmd); + init_cxl_cap(cxl); + cxl_core->region.noncached = info->noncached_region; return 0; @@ -266,6 +281,9 @@ int vfio_cxl_core_enable(struct vfio_cxl_core_device *cxl, if (ret) return ret; + pci->is_cxl = true; + pci->comp_reg_bar = cxl->comp_reg_bar; + ret = vfio_pci_core_enable(pci); if (ret) goto err_pci_core_enable; diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 502880e927fc..5f8334748841 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -483,7 +483,12 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) goto out_power; /* If reset fails because of the device lock, fail this path entirely */ - ret = pci_try_reset_function(pdev); + if (!vdev->is_cxl) + ret = pci_try_reset_function(pdev); + else + /* TODO: CXL reset support is on-going. */ + ret = -ENODEV; + if (ret == -EAGAIN) goto out_disable_device; @@ -618,8 +623,12 @@ void vfio_pci_core_disable(struct vfio_pci_core_device *vdev) if (!vdev->barmap[bar]) continue; pci_iounmap(pdev, vdev->barmap[bar]); - pci_release_selected_regions(pdev, 1 << bar); vdev->barmap[bar] = NULL; + + if (vdev->is_cxl && i == vdev->comp_reg_bar) + continue; + + pci_release_selected_regions(pdev, 1 << bar); } list_for_each_entry_safe(dummy_res, tmp, @@ -960,6 +969,15 @@ static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, if (vdev->reset_works) info.flags |= VFIO_DEVICE_FLAGS_RESET; + if (vdev->is_cxl) { + ret = vfio_info_add_capability(&caps, &vdev->cxl_cap.header, + sizeof(vdev->cxl_cap)); + if (ret) + return ret; + + info.flags |= VFIO_DEVICE_FLAGS_CXL; + } + info.num_regions = VFIO_PCI_NUM_REGIONS + vdev->num_regions; info.num_irqs = VFIO_PCI_NUM_IRQS; @@ -1752,14 +1770,21 @@ int vfio_pci_core_mmap(struct vfio_device *core_vdev, struct vm_area_struct *vma * we need to request the region and the barmap tracks that. */ if (!vdev->barmap[index]) { + int bars; + + if (vdev->is_cxl && vdev->comp_reg_bar == index) + bars = 0; + else + bars = 1 << index; + ret = pci_request_selected_regions(pdev, - 1 << index, "vfio-pci"); + bars, "vfio-pci"); if (ret) return ret; vdev->barmap[index] = pci_iomap(pdev, index, 0); if (!vdev->barmap[index]) { - pci_release_selected_regions(pdev, 1 << index); + pci_release_selected_regions(pdev, bars); return -ENOMEM; } } diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 6192788c8ba3..057cd0c69f2a 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -201,19 +201,24 @@ EXPORT_SYMBOL_GPL(vfio_pci_core_do_io_rw); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar) { struct pci_dev *pdev = vdev->pdev; - int ret; + int bars, ret; void __iomem *io; if (vdev->barmap[bar]) return 0; - ret = pci_request_selected_regions(pdev, 1 << bar, "vfio"); + if (vdev->is_cxl && vdev->comp_reg_bar == bar) + bars = 0; + else + bars = 1 << bar; + + ret = pci_request_selected_regions(pdev, bars, "vfio"); if (ret) return ret; io = pci_iomap(pdev, bar, 0); if (!io) { - pci_release_selected_regions(pdev, 1 << bar); + pci_release_selected_regions(pdev, bars); return -ENOMEM; } diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 8293910e0a96..0a354c7788b3 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -82,6 +82,9 @@ struct vfio_pci_core_device { bool needs_pm_restore:1; bool pm_intx_masked:1; bool pm_runtime_engaged:1; + bool is_cxl:1; + int comp_reg_bar; + struct vfio_device_info_cap_cxl cxl_cap; struct pci_saved_state *pci_saved_state; struct pci_saved_state *pm_save; int ioeventfds_nr; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 95be987d2ed5..0a9968cd6601 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -214,6 +214,7 @@ struct vfio_device_info { #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* Device supports CXL */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ __u32 cap_offset; /* Offset within info struct of first cap */ @@ -256,6 +257,15 @@ struct vfio_device_info_cap_pci_atomic_comp { __u32 reserved; }; +#define VFIO_DEVICE_INFO_CAP_CXL 6 +struct vfio_device_info_cap_cxl { + struct vfio_info_cap_header header; + __u8 hdm_count; + __u8 hdm_reg_bar_index; + __u64 hdm_reg_size; + __u64 hdm_reg_offset; +}; + /** * VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8, * struct vfio_region_info) -- 2.25.1