From: <mhonap@nvidia.com>
To: <aniketa@nvidia.com>, <ankita@nvidia.com>,
<alwilliamson@nvidia.com>, <vsethi@nvidia.com>, <jgg@nvidia.com>,
<mochs@nvidia.com>, <skolothumtho@nvidia.com>,
<alejandro.lucero-palau@amd.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>, <jgg@ziepe.ca>,
<yishaih@nvidia.com>, <kevin.tian@intel.com>
Cc: <cjia@nvidia.com>, <kwankhede@nvidia.com>, <targupta@nvidia.com>,
<zhiw@nvidia.com>, <kjaju@nvidia.com>,
<linux-kernel@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<kvm@vger.kernel.org>, <mhonap@nvidia.com>
Subject: [RFC v2 05/15] cxl: introduce cxl_get_committed_regions()
Date: Tue, 9 Dec 2025 22:20:09 +0530 [thread overview]
Message-ID: <20251209165019.2643142-6-mhonap@nvidia.com> (raw)
In-Reply-To: <20251209165019.2643142-1-mhonap@nvidia.com>
From: Zhi Wang <zhiw@nvidia.com>
The kernel CXL core can discover the configured and committed CXL regions
from BIOS or firmware, respect its configuration and create the related
kernel CXL core data structures without configuring and committing the CXL
region.
However, those information are kept within the kernel CXL core. A type-2
device can have the same usage and a type-2 driver would like to know
about it before creating the CXL regions.
Introduce cxl_get_committed_regions() for a type-2 driver to discover the
committed regions.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
Signed-off-by: Manish Honap <mhonap@nvidia.com>
---
drivers/cxl/core/region.c | 73 +++++++++++++++++++++++++++++++++++++++
include/cxl/cxl.h | 1 +
2 files changed, 74 insertions(+)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index e89a98780e76..6c368b4641f1 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -2785,6 +2785,79 @@ int cxl_get_region_range(struct cxl_region *region, struct range *range)
}
EXPORT_SYMBOL_NS_GPL(cxl_get_region_range, "CXL");
+struct match_region_info {
+ struct cxl_memdev *cxlmd;
+ struct cxl_region **cxlrs;
+ int nr_regions;
+};
+
+static int match_region_by_device(struct device *match, void *data)
+{
+ struct match_region_info *info = data;
+ struct cxl_endpoint_decoder *cxled;
+ struct cxl_memdev *cxlmd;
+ struct cxl_region_params *p;
+ struct cxl_region *cxlr;
+ int i;
+
+ if (!is_cxl_region(match))
+ return 0;
+
+ lockdep_assert_held(&cxl_rwsem.region);
+ cxlr = to_cxl_region(match);
+ p = &cxlr->params;
+
+ if (p->state != CXL_CONFIG_COMMIT)
+ return 0;
+
+ for (i = 0; i < p->nr_targets; i++) {
+ void *cxlrs;
+
+ cxled = p->targets[i];
+ cxlmd = cxled_to_memdev(cxled);
+
+ if (info->cxlmd != cxlmd)
+ continue;
+
+ cxlrs = krealloc(info->cxlrs, sizeof(cxlr) * (info->nr_regions + 1),
+ GFP_KERNEL);
+ if (!cxlrs) {
+ kfree(info->cxlrs);
+ return -ENOMEM;
+ }
+ info->cxlrs = cxlrs;
+
+ info->cxlrs[info->nr_regions++] = cxlr;
+ }
+
+ return 0;
+}
+
+int cxl_get_committed_regions(struct cxl_memdev *cxlmd, struct cxl_region ***cxlrs, int *num)
+{
+ struct match_region_info info = {0};
+ int ret = 0;
+
+ ret = down_write_killable(&cxl_rwsem.region);
+ if (ret)
+ return ret;
+
+ info.cxlmd = cxlmd;
+
+ ret = bus_for_each_dev(&cxl_bus_type, NULL, &info, match_region_by_device);
+ if (ret) {
+ kfree(info.cxlrs);
+ } else {
+ *cxlrs = info.cxlrs;
+ *num = info.nr_regions;
+ }
+
+ up_write(&cxl_rwsem.region);
+
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_get_committed_regions, "CXL");
+
static ssize_t __create_region_show(struct cxl_root_decoder *cxlrd, char *buf)
{
return sysfs_emit(buf, "region%u\n", atomic_read(&cxlrd->region_id));
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index e3bf8cf0b6d6..0a1f245557f4 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -295,5 +295,6 @@ int cxl_get_region_range(struct cxl_region *region, struct range *range);
int cxl_get_hdm_reg_info(struct cxl_dev_state *cxlds, u64 *count, u64 *offset,
u64 *size);
int cxl_find_comp_regblock_offset(struct pci_dev *pdev, u64 *offset);
+int cxl_get_committed_regions(struct cxl_memdev *cxlmd, struct cxl_region ***cxlrs, int *num);
#endif /* __CXL_CXL_H__ */
--
2.25.1
next prev parent reply other threads:[~2025-12-09 16:51 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-09 16:50 [RFC v2 00/15] vfio: introduce vfio-cxl to support CXL type-2 accelerator passthrough Hello all, mhonap
2025-12-09 16:50 ` [RFC v2 01/15] cxl: factor out cxl_await_range_active() and cxl_media_ready() mhonap
2025-12-22 12:21 ` Jonathan Cameron
2025-12-09 16:50 ` [RFC v2 02/15] cxl: introduce cxl_get_hdm_reg_info() mhonap
2025-12-09 16:50 ` [RFC v2 03/15] cxl: introduce cxl_find_comp_reglock_offset() mhonap
2025-12-09 16:50 ` [RFC v2 04/15] cxl: introduce devm_cxl_del_memdev() mhonap
2025-12-09 16:50 ` mhonap [this message]
2025-12-22 12:31 ` [RFC v2 05/15] cxl: introduce cxl_get_committed_regions() Jonathan Cameron
2025-12-09 16:50 ` [RFC v2 06/15] vfio/cxl: introduce vfio-cxl core preludes mhonap
2025-12-22 13:54 ` Jonathan Cameron
2025-12-09 16:50 ` [RFC v2 07/15] vfio/cxl: expose CXL region to the userspace via a new VFIO device region mhonap
2025-12-11 16:06 ` Dave Jiang
2025-12-11 17:31 ` Manish Honap
2025-12-11 18:01 ` Dave Jiang
2025-12-22 14:00 ` Jonathan Cameron
2025-12-09 16:50 ` [RFC v2 08/15] vfio/cxl: discover precommitted CXL region mhonap
2025-12-22 14:09 ` Jonathan Cameron
2025-12-09 16:50 ` [RFC v2 09/15] vfio/cxl: introduce vfio_cxl_core_{read, write}() mhonap
2025-12-09 16:50 ` [RFC v2 10/15] vfio/cxl: introduce the register emulation framework mhonap
2025-12-09 16:50 ` [RFC v2 11/15] vfio/cxl: introduce the emulation of HDM registers mhonap
2025-12-11 18:13 ` Dave Jiang
2025-12-09 16:50 ` [RFC v2 12/15] vfio/cxl: introduce the emulation of CXL configuration space mhonap
2025-12-09 16:50 ` [RFC v2 13/15] vfio/pci: introduce CXL device awareness mhonap
2025-12-09 16:50 ` [RFC v2 14/15] vfio/cxl: VFIO variant driver for QEMU CXL accel device mhonap
2025-12-09 16:50 ` [RFC v2 15/15] cxl/mem: Fix NULL pointer deference in memory device paths mhonap
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