[PATCH v2 3/4] arm64: dts: intel: agilex5: Add dma-ranges, address and size cells to dma node

Khairul Anuar Romli
2025-12-08T01:58:03Z

Update the compatible string for the DMA controller nodes in the Agilex5
device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
"altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
to initialize properly.

This change enables the use of platform-specific features and constraints
in the driver, such as setting a 40-bit DMA addressable mask through
dma-ranges, which is required for Agilex5. It also aligns with the updated
device tree bindings and driver support for this compatible string.

Address-cells and size-cells are also defined along with dma-ranges to
ensure of_base driver does not causing kernel panic during boot up.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
- Rename the from add platform specific to add dma-ranges, address
and size cells.
- Define address-cells and size-cells for dmac0 and dmac1
- Add dma-ranges for agilex5 for 40-bit
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 06f98667499b..1983869274e7 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -336,8 +336,11 @@ ocram: sram@0 {
};

dmac0: dma-controller@10db0000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "altr,agilex5-axi-dma",
+ "snps,axi-dma-1.01a";
reg = <0x10db0000 0x500>;
+ #address-cells = <1>;
+ #size-cells = <2>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
@@ -351,11 +354,15 @@ dmac0: dma-controller@10db0000 {
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 8>;
+ dma-ranges = <0x00 0x00 0x00000100 0x00000000>;
};

dmac1: dma-controller@10dc0000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "altr,agilex5-axi-dma",
+ "snps,axi-dma-1.01a";
reg = <0x10dc0000 0x500>;
+ #address-cells = <1>;
+ #size-cells = <2>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
@@ -369,6 +376,7 @@ dmac1: dma-controller@10dc0000 {
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 9>;
+ dma-ranges = <0x00 0x00 0x00000100 0x00000000>;
};

rst: rstmgr@10d11000 {
--
2.43.7