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Wed, 10 Dec 2025 11:16:11 +0100 From: Christophe Parant To: , , , CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Subject: [PATCH RESEND v2 00/11] Rework and fix STM32MP15x PHYTEC dts Date: Wed, 10 Dec 2025 11:16:00 +0100 Message-ID: <20251210101611.27008-1-c.parant@phytec.fr> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 10.12.2025 11:16:11, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 10.12.2025 11:16:11 X-TNEFEvaluated: 1 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PEPF00028D09:EE_|DB9P195MB1492:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e30ad56-64f5-45ac-d435-08de37d5253a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 10:16:12.4633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e30ad56-64f5-45ac-d435-08de37d5253a X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Postix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D09.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9P195MB1492 This patch series rename and reorganize the STM32MP15x PHYTEC baseboard (phyBOARD-Sargas) and SoM (phyCORE-STM32MP15x) device tree files. Indeed, the current device tree naming and organization is not really consistent as it does not align with others STM32MP boards (use common dtsi file as much as possible, use one dtsi for SoM and one dtsi for baseboard). The series also fixes some important pinctrl issues and minor one (coding style). Additional pinctrl is also added for the optionnal interfaces that are not enabled by default (FMC, LTDC, DCMI, PWM). Changes in v2: - Rebase on v6.16-rc5 - Rework Patch 3 (stm32.yaml): for board description, keep "compatible" string identifiers as before to not break ABI. But use "enum" type instead of "const" for the SoM and phyBOARD indentifiers. Christophe Parant (11): ARM: dts: stm32: phycore-stm32mp15: Rename device tree files ARM: dts: stm32: phyboard-sargas: Introduce SoM device tree dt-bindings: arm: stm32: Modify STM32MP15x Phytec board items types ARM: dts: stm32: Add new pinmux groups for phyboard-sargas and phycore ARM: dts: stm32: phyboard-sargas: Fix uart4 and sai2 pinctrl ARM: dts: stm32: phycore-stm32mp15: qspi: Fix memory map and pinctrl ARM: dts: stm32: phycore-stm32mp15: Add dummy memory-node ARM: dts: stm32: phyboard-sargas: Move aliases from dts to dtsi ARM: dts: stm32: phycore-stm32mp15: Disable optional SoM peripherals ARM: dts: stm32: phyboard-sargas and phycore: Fix coding style issues ARM: dts: stm32: phyboard-sargas and phycore: Add optional interfaces .../devicetree/bindings/arm/stm32/stm32.yaml | 8 +- arch/arm/boot/dts/st/Makefile | 2 +- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 164 +++++++++ ...ts =3D> stm32mp157c-phyboard-sargas-rdk.dts} | 24 +- .../dts/st/stm32mp15xx-phyboard-sargas.dtsi | 285 +++++++++++++++ ...-som.dtsi =3D> stm32mp15xx-phycore-som.dtsi} | 344 ++++-------------- 6 files changed, 525 insertions(+), 302 deletions(-) rename arch/arm/boot/dts/st/{stm32mp157c-phycore-stm32mp1-3.dts =3D> stm32= mp157c-phyboard-sargas-rdk.dts} (58%) create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi rename arch/arm/boot/dts/st/{stm32mp157c-phycore-stm32mp15-som.dtsi =3D> s= tm32mp15xx-phycore-som.dtsi} (53%) --=20 2.34.1