[PATCH 0/7] Add Diamond Rapids uncore support

[Zide Chen <zide.chen@intel.com>]

Similar to Intel Sapphire Rapids, Diamond Rapids relies on discovery
tables for uncore enumeration.  Key differences and additions include:

- DMR may have two Integrated I/O and Memory Hub (IMH) dies, which are
  separate from the compute tile (CBB) dies.  Each CBB die and each IMH
  die has its own dedicated discovery table.

- Unlike prior CPUs that retrieve the global discovery table portal
  exclusively through either PCI or MSR, DMR uses PCI for IMH PMON
  discovery and MSR for CBB PMON discovery

- DMR introduces several new PMON types, including SCA, HAMVF, D2D_ULA,
  UBR, PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6.

- Unlike SPR, IIO free-running counters in DMR are MMIO-based.

Zide Chen (7):
  perf/x86/intel/uncore: Add dual PCI/MSR discovery support
  perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids
  perf/x86/intel/uncore: Add CBB PMON support for Diamond Rapids
  perf/x86/intel/uncore: Add freerunning event descriptor helper macro
  perf/x86/intel/uncore: Support IIO free-running counters on DMR
  perf/x86/intel/uncore: Update DMR uncore constraints preliminarily
  perf pmu: Relax uncore wildcard matching to allow numeric suffix

 arch/x86/events/intel/uncore.c           |  39 +-
 arch/x86/events/intel/uncore.h           |   3 +
 arch/x86/events/intel/uncore_discovery.c |  42 +-
 arch/x86/events/intel/uncore_discovery.h |   6 +-
 arch/x86/events/intel/uncore_snbep.c     | 558 ++++++++++++++++++++---
 tools/perf/util/pmu.c                    |  14 +-
 6 files changed, 548 insertions(+), 114 deletions(-)

-- 
2.52.0