From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 156B62D7DE9 for ; Sun, 14 Dec 2025 08:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765702090; cv=none; b=EUw3rqKFb5X8m4HM2Ui8LJTrdfyyqgkSy/TivgL6OcqSk5UEsQ6lOcmpA+k1Wn8qXVElrh943abfI+wgWrTmphon4ND1VCKWNauXCGhN6XHRN9LSdowfsqo0C6oHJn/WDWl/9p6rw9NllqmrzQipVw0ylEG7Ca9BJUmNwY9qV5Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765702090; c=relaxed/simple; bh=cRW+R0xUm7u3A292zSBZqTaqiogVhKRsZVmPlgAAHHw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mAaQh0TMEPMixf8Tuv066w6uDUht1ir6exsQm9X3MMA8XIaxVD0QSyc9sXlNufYbW+ZAnCEJcv81Qd0lLX8gZ6MFWrBu/8afz6wCB7knf5EWMvMNoEBy168KbCXsrRy5lPPtuRzIAKLGbdcoG4Pqlg6MG05SaoLBnrP6MftTF4s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YerMSGbi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YerMSGbi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 65C88C4CEF1; Sun, 14 Dec 2025 08:48:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765702087; bh=cRW+R0xUm7u3A292zSBZqTaqiogVhKRsZVmPlgAAHHw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YerMSGbiUqp9Fmdfw4iX08gROvCz9q6pwLXdYqyXR7ag81ZEz2hilvtm21n5V4gG3 yc3WS60HkPOTFy/XSk+BvPBVz8P0p/76c9MGPPfv/flS9YiacgPGyMN+PwKqEboE+V xrvt+pAQuKSn22x1ngfQTskDjQ8lpmJs/Be94khDzugugsTUsx5bewLwYbmZB3sNpZ iNvAzm8+x/npfwOVeMVktYY6hcmrxJCUA8CK+wTYpselNBVIMcIYqh3jTpXt+ule/J Bcpi1Y0cBzCg+i5ODEvAa8O+gZRUo6mwDAKu1zww/Amg0Znwrv1GivP1j31Z8Bfz+e nYeIuWtDuiPHA== From: Ingo Molnar To: linux-kernel@vger.kernel.org Cc: Ingo Molnar , "Ahmed S . Darwish" , Andrew Cooper , Ard Biesheuvel , Arnd Bergmann , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Arnd Bergmann Subject: [PATCH 12/15] x86: Remove !CONFIG_X86_TSC code Date: Sun, 14 Dec 2025 09:47:00 +0100 Message-ID: <20251214084710.3606385-13-mingo@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214084710.3606385-1-mingo@kernel.org> References: <20251214084710.3606385-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Now that the Kconfig space always enables CONFIG_X86_TSC (on x86), remove !CONFIG_X86_TSC code. We still keep the Kconfig option to catch any eventual code still pending in maintainer or non-mainline trees, and it's also still possible to disable TSC support runtime. Signed-off-by: Ingo Molnar Reviewed-by: Arnd Bergmann Acked-by: Dave Hansen Cc: Ahmed S . Darwish Cc: Andrew Cooper Cc: Ard Biesheuvel Cc: H . Peter Anvin Cc: John Ogness Cc: Linus Torvalds Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20250425084216.3913608-13-mingo@kernel.org --- arch/x86/include/asm/timex.h | 3 +-- arch/x86/include/asm/trace_clock.h | 8 -------- arch/x86/include/asm/tsc.h | 13 +------------ arch/x86/kernel/Makefile | 4 ++-- arch/x86/kernel/i8253.c | 2 +- arch/x86/kernel/tsc.c | 13 ------------- 6 files changed, 5 insertions(+), 38 deletions(-) diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h index 956e4145311b..6e57e3c0fdd2 100644 --- a/arch/x86/include/asm/timex.h +++ b/arch/x86/include/asm/timex.h @@ -7,8 +7,7 @@ static inline unsigned long random_get_entropy(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) && - !cpu_feature_enabled(X86_FEATURE_TSC)) + if (!cpu_feature_enabled(X86_FEATURE_TSC)) return random_get_entropy_fallback(); return rdtsc(); } diff --git a/arch/x86/include/asm/trace_clock.h b/arch/x86/include/asm/trace_clock.h index 7061a5650969..1efab284c32a 100644 --- a/arch/x86/include/asm/trace_clock.h +++ b/arch/x86/include/asm/trace_clock.h @@ -5,17 +5,9 @@ #include #include -#ifdef CONFIG_X86_TSC - extern u64 notrace trace_clock_x86_tsc(void); # define ARCH_TRACE_CLOCKS \ { trace_clock_x86_tsc, "x86-tsc", .in_ns = 0 }, -#else /* !CONFIG_X86_TSC */ - -#define ARCH_TRACE_CLOCKS - -#endif - #endif /* _ASM_X86_TRACE_CLOCK_H */ diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 4f7f09f50552..4d2d2f21ff06 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -76,8 +76,7 @@ extern void disable_TSC(void); static inline cycles_t get_cycles(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) && - !cpu_feature_enabled(X86_FEATURE_TSC)) + if (!cpu_feature_enabled(X86_FEATURE_TSC)) return 0; return rdtsc(); } @@ -94,25 +93,15 @@ extern unsigned long native_calibrate_tsc(void); extern unsigned long long native_sched_clock_from_tsc(u64 tsc); extern int tsc_clocksource_reliable; -#ifdef CONFIG_X86_TSC extern bool tsc_async_resets; -#else -# define tsc_async_resets false -#endif /* * Boot-time check whether the TSCs are synchronized across * all CPUs/cores: */ -#ifdef CONFIG_X86_TSC extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); extern void tsc_verify_tsc_adjust(bool resume); extern void check_tsc_sync_target(void); -#else -static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } -static inline void tsc_verify_tsc_adjust(bool resume) { } -static inline void check_tsc_sync_target(void) { } -#endif extern int notsc_setup(char *); extern void tsc_save_sched_clock_state(void); diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index bc184dd38d99..19ebb67df142 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -94,7 +94,7 @@ apm-y := apm_32.o obj-$(CONFIG_APM) += apm.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smpboot.o -obj-$(CONFIG_X86_TSC) += tsc_sync.o +obj-y += tsc_sync.o obj-$(CONFIG_SMP) += setup_percpu.o obj-$(CONFIG_X86_MPPARSE) += mpparse.o obj-y += apic/ @@ -103,7 +103,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_FUNCTION_TRACER) += ftrace_$(BITS).o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o -obj-$(CONFIG_X86_TSC) += trace_clock.o +obj-y += trace_clock.o obj-$(CONFIG_TRACING) += trace.o obj-$(CONFIG_RETHOOK) += rethook.o obj-$(CONFIG_VMCORE_INFO) += vmcore_info_$(BITS).o diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c index cb9852ad6098..0b991035f127 100644 --- a/arch/x86/kernel/i8253.c +++ b/arch/x86/kernel/i8253.c @@ -31,7 +31,7 @@ struct clock_event_device *global_clock_event; */ static bool __init use_pit(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) + if (!boot_cpu_has(X86_FEATURE_TSC)) return true; /* This also returns true when APIC is disabled */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 7d3e13e14eab..5ad2c803d5a1 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -297,24 +297,11 @@ int check_tsc_unstable(void) } EXPORT_SYMBOL_GPL(check_tsc_unstable); -#ifdef CONFIG_X86_TSC int __init notsc_setup(char *str) { mark_tsc_unstable("boot parameter notsc"); return 1; } -#else -/* - * disable flag for tsc. Takes effect by clearing the TSC cpu flag - * in cpu/common.c - */ -int __init notsc_setup(char *str) -{ - setup_clear_cpu_cap(X86_FEATURE_TSC); - return 1; -} -#endif - __setup("notsc", notsc_setup); static int no_sched_irq_time; -- 2.51.0