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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fbab2d3b6sm12954173f8f.23.2025.12.14.05.39.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 05:39:26 -0800 (PST) Date: Sun, 14 Dec 2025 13:39:25 +0000 From: David Laight To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, "Ahmed S . Darwish" , Andrew Cooper , Ard Biesheuvel , Arnd Bergmann , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Thomas Gleixner Subject: Re: [PATCH -v3 0/15] x86: Remove support for TSC-less and CX8-less CPUs Message-ID: <20251214133925.1e80f851@pumpkin> In-Reply-To: <20251214084710.3606385-1-mingo@kernel.org> References: <20251214084710.3606385-1-mingo@kernel.org> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Sun, 14 Dec 2025 09:46:48 +0100 Ingo Molnar wrote: >... > > Original -v1 announcement: > > In the x86 architecture we have various complicated hardware emulation > facilities on x86-32 to support ancient 32-bit CPUs that very very few > people are using with modern kernels. This compatibility glue is sometimes > even causing problems that people spend time to resolve, which time could > be spent on other things. > > As Linus recently remarked: > > > I really get the feeling that it's time to leave i486 support behind. > > There's zero real reason for anybody to waste one second of > > development effort on this kind of issue. > > This series increases minimum kernel support features to include TSC and > CX8 (CMPXCHG8B) hardware support, which removes 486 (and derivatives) support > and early-586 (and derivatives) support. Two questions: 1) What happens if you try to boot the kernel on an old system? Is there an early check that makes it fail 'moderately gracefully'? 2) Is it worth also dropping support for cpu that don't support CMOV. I think that is 'Pentium Pro' and 'K7' rather than 'Pentium' and 'K5'. That simplifies some asm code. 'masked' user access would really need it (and a guard page). The 'long nop' get added at the same time. It is also (almost certainly) new enough that the 'bit scan' instructions are guaranteed to leave the the destination unchanged if the source is zero (dropping just 486 may be enough for that). Moving the minimum cpu to P-Pro now will probably save another similar change in the near future. David