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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8beeb5d6952sm186866985a.3.2025.12.18.07.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 07:12:39 -0800 (PST) From: Alex Elder To: dlan@gentoo.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org Cc: ziyao@disroot.org, aurelien@aurel32.net, johannes@erdfelt.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, guodong@riscstar.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 0/5] Introduce SpacemiT K1 PCIe phy support Date: Thu, 18 Dec 2025 09:12:26 -0600 Message-ID: <20251218151235.454997-1-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series introduces a PHY driver to support PCIe on the SpacemiT K1 SoC. The PCIe controller implementation is derived from a Synopsys DesignWare PCIe IP. The PHY driver supports one combination PCIe/USB PHY as well as two PCIe-only PHYs. The combo PHY port uses one PCIe lane, and the other two ports each have two lanes. All PCIe ports operate at 5 GT/second. The PCIe PHYs must be configured using a value that can only be determined using the combo PHY, operating in PCIe mode. To allow that PHY to be used for USB, the needed calibration step is performed by the PHY driver automatically at probe time. Once this step is done, the PHY can be used for either PCIe or USB. The PCIe controller driver that was included in earlier versions of this series has already been accepted upstream: a812b09a6b599 ("dt-bindings: pci: spacemit: Introduce PCIe host controller") ff64e078e45fa ("PCI: spacemit: Add SpacemiT PCIe host driver") However this series still includes devicetree patches to enable the PCIe controller (along with the PHYs). The patches that remain in version 7 of this series are unchanged; they are simply rebased on top of Linux v6.19-rc1. The first two patches are the DT bindings for the PCIe and combo PCIe/USB PHY. The third is the PHY driver, and the last two are devicetree updates to enable the PCIe controller and PHYs. -Alex Alex Elder (5): dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY dt-bindings: phy: spacemit: Introduce PCIe PHY phy: spacemit: Introduce PCIe/combo PHY riscv: dts: spacemit: Add a PCIe regulator riscv: dts: spacemit: PCIe and PHY-related updates .../bindings/phy/spacemit,k1-combo-phy.yaml | 114 +++ .../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 ++ .../boot/dts/spacemit/k1-bananapi-f3.dts | 44 ++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 + arch/riscv/boot/dts/spacemit/k1.dtsi | 176 +++++ drivers/phy/Kconfig | 11 + drivers/phy/Makefile | 1 + drivers/phy/phy-spacemit-k1-pcie.c | 670 ++++++++++++++++++ 8 files changed, 1120 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 -- 2.48.1