Re: [PATCH v4 3/3] dma: dw-axi-dmac: Add support for Agilex5 and dynamic bus width

[Rob Herring <robh@kernel.org>]

On Wed, Dec 17, 2025 at 07:26:18AM +0800, Khairul Anuar Romli wrote:
> Add device tree compatible string support for the Altera Agilex5 AXI DMA
> controller.
> 
> Use common get "dma-ranges" property and calculate the actual number of
> addressable bits (bus width) for the DMA engine. This calculated value is
> then used to set the coherent mask via 'dma_set_mask_and_coherent()',
> allowing the driver to correctly handle devices with bus widths less than
> 64 bits. Initialize the addressable bits default to 64 if 'dma-ranges' is
> not specified or cannot be parsed.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v4:
> 	- Simplify the code to use common code to get dma ranges.
> 	- Narrow the code changes on hw_init.
> Changes in v3:
> 	- Refactor the code to align with dma controller device node move
> 	  to 1 level down.
> Changes in v2:
> 	- Add driver implementation to set the DMA BIT MAST to 40 based on
> 	  dma-ranges defined in DT.
> 	- Add glue for driver and DT.
> ---
>  drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 16 +++++++++++++++-
>  drivers/dma/dw-axi-dmac/dw-axi-dmac.h          |  1 +
>  2 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index b23536645ff7..ac67c18a05c0 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -12,6 +12,7 @@
>  #include <linux/device.h>
>  #include <linux/dmaengine.h>
>  #include <linux/dmapool.h>
> +#include <linux/dma-direct.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/err.h>
>  #include <linux/interrupt.h>
> @@ -264,14 +265,25 @@ static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
>  
>  static void axi_dma_hw_init(struct axi_dma_chip *chip)
>  {
> +	const struct bus_dma_region *map = NULL;
> +	unsigned int addressable_bits = 64;
>  	int ret;
> +	u64 max_bus;
>  	u32 i;
>  
>  	for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
>  		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
>  		axi_chan_disable(&chip->dw->chan[i]);
>  	}
> -	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
> +
> +	ret = of_dma_get_range(chip->dev->of_node, &map);
> +	if (!ret) {
> +		max_bus = map->dma_start + map->size - 1;
> +		addressable_bits = fls64(max_bus);
> +	}
> +
> +	dev_dbg(chip->dev, "Addressable bus width: %u\n", addressable_bits);
> +	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(addressable_bits));

I'm pretty sure you don't need to do any of this. The core will merge 
the device's mask with the bus ranges.

Rob