Re: [PATCH] PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

[Bjorn Helgaas <helgaas@kernel.org>]

On Sat, Dec 27, 2025 at 09:58:28AM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 26, 2025 at 05:39:55PM -0600, Bjorn Helgaas wrote:
> > [+cc Val]
> > 
> > On Wed, Nov 26, 2025 at 01:47:18PM +0530, Manivannan Sadhasivam wrote:
> > > From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > 
> > > Though I couldn't confirm the ASPM L0s support with the Qcom hardware team,
> > > bug report from Dmitry suggests that L0s is broken on this legacy SoC.
> > > Hence, clear the L0s CAP for the Root Ports in this SoC.
> ...

> > This looks like possible v6.19 material since it's a regression
> > and Dmitry reported random resets that are impossible to debug?
> 
> Yes. I was about to ping you offline the list of v6.19 materials
> once you got back from vacation.

Thanks, I moved this to for-linus for v6.19 and updated
pci/controller/dwc-qcom accordingly.

> > For now I moved this to the beginning of pci/controller/dwc-qcom since
> > it sounds like the PERST# series will be updated.
> > 
> > > Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config,
> > > call it from qcom_pcie_host_init() instead.
> > > 
> > > Reported-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > > Closes: https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > ---
> > >  drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 805edbbfe7eb..25399d47fc40 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -1088,7 +1088,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
> > >  		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
> > >  				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
> > >  
> > > -	qcom_pcie_clear_aspm_l0s(pcie->pci);
> > >  	qcom_pcie_clear_hpc(pcie->pci);
> > >  
> > >  	return 0;
> > > @@ -1350,6 +1349,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
> > >  			goto err_disable_phy;
> > >  	}
> > >  
> > > +	qcom_pcie_clear_aspm_l0s(pcie->pci);
> > > +
> > >  	qcom_ep_reset_deassert(pcie);
> > >  
> > >  	if (pcie->cfg->ops->config_sid) {
> > > @@ -1486,6 +1487,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
> > >  
> > >  static const struct qcom_pcie_cfg cfg_2_3_2 = {
> > >  	.ops = &ops_2_3_2,
> > > +	.no_l0s = true,
> > >  };
> > >  
> > >  static const struct qcom_pcie_cfg cfg_2_3_3 = {
> > > -- 
> > > 2.48.1
> > > 
> 
> -- 
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