From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B6F4307AD5 for ; Mon, 5 Jan 2026 16:47:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767631669; cv=none; b=AoQsHHptqJhPY1oCGJ7E6/aEiyoHttITMALwKDO37RSElfCY20IEKISBseXEA9Mf9BT4pO9bxgmYBrEhp6vUq3BCLMppMvb/PY2WMGB5dpCVk7MmdA85dOyFQEnS/2ZE7eU/QOWJ63OMqSrPf3MTWnUWb0zuBIAa/NzZOBPRStw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767631669; c=relaxed/simple; bh=jB79SVycgpWUHqu56CTIEX8Dr2rt+TWxNn3oa0hK3gA=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HLk7rUxHZ96lFhTl26JuMGUEC+eHDGhed/70hY0PbytYjd8bGEbr4QjdPzSbuJeeiyupRuR6qCiALsBgi9AmJSgk2P3IRE+IqzHtpFRPg4DY4DbY8GJMrK3kvTuoZEVmQ5zKQwU2NVhCfG4aun+Wb30YyOq/CbipB6Z5OQrDrV4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.224.107]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4dlKwW0qpSzHnGhT; Tue, 6 Jan 2026 00:47:39 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id A183B40570; Tue, 6 Jan 2026 00:47:41 +0800 (CST) Received: from localhost (10.126.174.38) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Mon, 5 Jan 2026 16:47:40 +0000 Date: Mon, 5 Jan 2026 16:47:38 +0000 From: Jonathan Cameron To: Ben Horgan CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 06/45] KVM: arm64: Make MPAMSM_EL1 accesses UNDEF Message-ID: <20260105164738.0000792f@huawei.com> In-Reply-To: <20251219181147.3404071-7-ben.horgan@arm.com> References: <20251219181147.3404071-1-ben.horgan@arm.com> <20251219181147.3404071-7-ben.horgan@arm.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500009.china.huawei.com (7.191.174.84) To dubpeml100005.china.huawei.com (7.214.146.113) On Fri, 19 Dec 2025 18:11:08 +0000 Ben Horgan wrote: > The MPAMSM_EL1 controls the MPAM labeling for an SMCU, Streaming Mode > Compute Unit. As there is on MPAM support in kvm, make sure MPAMSM_EL1 > accesses trigger an UNDEF. > > The range of valid configurations for the PARTID and PMG in MPAMSM_EL1 is > not currently specified in Arm Architectural Reference Manual but the > architect has confirmed that it is intended to be the same as that for the > cpu configuration in the MPAMy_ELx registers. Good to know but I'm not seeing why it matters in this patch. Perhaps a little more on that? > > Signed-off-by: Ben Horgan Reviewed-by: Jonathan Cameron > --- > arch/arm64/kvm/sys_regs.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index c8fd7c6a12a1..72654ab984ee 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -3373,6 +3373,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { > > { SYS_DESC(SYS_MPAM1_EL1), undef_access }, > { SYS_DESC(SYS_MPAM0_EL1), undef_access }, > + { SYS_DESC(SYS_MPAMSM_EL1), undef_access }, > + > { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, > { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, >