From: Jakub Kicinski <kuba@kernel.org>
To: Yeounsu Moon <yyyynoom@gmail.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net v2] net: dlink: mask rx_coalesce/rx_timeout before writing RxDMAIntCtrl
Date: Mon, 5 Jan 2026 16:58:54 -0800 [thread overview]
Message-ID: <20260105165854.104e6c1d@kernel.org> (raw)
In-Reply-To: <20260103092904.44462-2-yyyynoom@gmail.com>
On Sat, 3 Jan 2026 18:29:05 +0900 Yeounsu Moon wrote:
> RxDMAIntCtrl encodes rx_coalesce in the low 16 bits
> and rx_timeout in the high 16 bits. If either value exceeds
> the field width, the current code may truncate the value and/or
> corrupt adjacent bits when programming the register.
>
> Mask both values to 16 bits so only the intended fields are written.
Realistically IDK if this is worth it.
Paolo suggested in discussion on v1 that error checking could introduce
a regression. If we take that concern seriously we can't change the
(buggy) behavior at all.
That said the overflow is on frames, for values > 64k and the ring is
256 so IDK how high values could possibly work here in the first place.
Given this driver is using module params to configure coalescing I'd
just leave this mess be. If you add ethtool configuration for
coalescing make sure to correctly bound-check it.
--
pw-bot: reject
next prev parent reply other threads:[~2026-01-06 0:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-03 9:29 [PATCH net v2] net: dlink: mask rx_coalesce/rx_timeout before writing RxDMAIntCtrl Yeounsu Moon
2026-01-06 0:58 ` Jakub Kicinski [this message]
2026-01-06 11:32 ` Yeounsu Moon
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