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From: Rob Herring <robh@kernel.org>
To: Charan Pedumuru <charan.pedumuru@gmail.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
Date: Mon, 5 Jan 2026 16:08:59 -0600	[thread overview]
Message-ID: <20260105220859.GA3498531-robh@kernel.org> (raw)
In-Reply-To: <20260103-ti-phy-v1-1-8c3f5e2cbd63@gmail.com>

On Sat, Jan 03, 2026 at 11:06:10AM +0000, Charan Pedumuru wrote:
> Convert TI OMAP Control PHY and PIPE3 PHY binding to YAML format.
> Changes during conversion:
> - Define a new pattern 'pciephy'and 'control-phy' to match nodes
>   defined in DT.
> 
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
>  .../bindings/phy/ti,control-phy-otghs.yaml         | 206 +++++++++++++++++++++
>  Documentation/devicetree/bindings/phy/ti-phy.txt   |  98 ----------
>  2 files changed, 206 insertions(+), 98 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
> new file mode 100644
> index 000000000000..830be2af5fb6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
> @@ -0,0 +1,206 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI PHYs for TI Platforms (OMAP Control PHY and PIPE3 PHY)
> +
> +maintainers:
> +  - Vinod Koul <vkoul@kernel.org>

No, this should be a TI person or someone with the h/w.

> +
> +description:
> +  This device tree binding describes the TI PHYs used in TI platforms.
> +  Two types of PHYs are supported.
> +  1. OMAP Control PHY - Simple control PHYs for power control
> +  2. PIPE3 PHY - High-speed PIPE3 PHYs for USB3, SATA, PCIe
> +
> +properties:
> +  $nodename:
> +    pattern: "^(pciephy|control-phy|usb3phy|phy)(@[0-9a-fA-F]+)?$"

Only phy, pcie-phy, or usb3-phy are valid node names.

A-F is not valid for unit-addresses either.

> +
> +  compatible:
> +    oneOf:
> +      - description: OMAP Control PHY compatibles
> +        items:
> +          enum:
> +            - ti,control-phy-otghs
> +            - ti,control-phy-usb2
> +            - ti,control-phy-pipe3
> +            - ti,control-phy-pcie
> +            - ti,control-phy-usb2-dra7
> +            - ti,control-phy-usb2-am437
> +      - description: PIPE3 high-speed PHY compatibles
> +        items:
> +          enum:
> +            - ti,phy-usb3
> +            - ti,phy-pipe3-sata
> +            - ti,phy-pipe3-pcie
> +            - ti,omap-usb3

IMO, these 2 bindings are completely unrelated and should be split to 2 
schema files.

> +
> +  reg:
> +    minItems: 1
> +    maxItems: 4
> +
> +  reg-names:
> +    oneOf:
> +      - description: OMAP Control PHY
> +        items:
> +          enum: [otghs_control, power, pcie_pcs, control_sma]
> +      - description: PIPE3 high-speed PHY
> +        items:
> +          enum: [phy_rx, phy_tx, pll_ctrl]

Here's one example why.

> +
> +  "#phy-cells":
> +    const: 0
> +
> +  clocks:
> +    minItems: 2
> +    maxItems: 7
> +
> +  clock-names:
> +    minItems: 2
> +    maxItems: 7
> +    items:
> +      enum: [wkupclk, sysclk, refclk, dpll_ref,
> +             dpll_ref_m2, phy-div, div-clk]
> +
> +# Optional Properties
> +  id:
> +    description:
> +      Instance ID for multiple instances of same PHY type.
> +      Used for multi-lane PCIe PHYs.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 1

There aren't any users of this that I see. Drop it (and note that in the 
commit msg).

> +
> +  syscon-phy-power:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      Phandle/offset pair to system control module register for PHY
> +      power on/off.
> +
> +  syscon-pllreset:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
> +      SATA_PLL_SOFT_RESET bit (SATA PHY only).
> +
> +  syscon-pcs:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      Phandle/offset pair to system control module for writing PCS delay value.
> +
> +  ctrl-module:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle of control module for PHY power on.
> +    deprecated: true

I believe all these phandle props only apply to the PIPE3 binding.

Rob

  reply	other threads:[~2026-01-05 22:09 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-03 11:06 [PATCH] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema Charan Pedumuru
2026-01-05 22:08 ` Rob Herring [this message]
2026-01-06 12:23   ` Charan Pedumuru

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