From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH v9 06/13] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos()
Date: Sat, 10 Jan 2026 12:46:51 +0100 [thread overview]
Message-ID: <20260110114705.681676-7-rrichter@amd.com> (raw)
In-Reply-To: <20260110114705.681676-1-rrichter@amd.com>
cxl_calc_interleave_pos() uses the endpoint decoder's HPA range to
determine its interleaving position. This requires the endpoint
decoders to be an SPA, which is not the case for systems that need
address translation.
Add a separate @hpa_range argument to function
cxl_calc_interleave_pos() to specify the address range. Now it is
possible to pass the SPA translated address range of an endpoint
decoder to function cxl_calc_interleave_pos().
Refactor only, no functional changes.
Patch is a prerequisite to implement address translation.
Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Tested-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/core/region.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 5ae77e9feb4d..60d2d1dae2aa 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1878,6 +1878,7 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
/**
* cxl_calc_interleave_pos() - calculate an endpoint position in a region
* @cxled: endpoint decoder member of given region
+ * @hpa_range: translated HPA range of the endpoint
*
* The endpoint position is calculated by traversing the topology from
* the endpoint to the root decoder and iteratively applying this
@@ -1890,11 +1891,11 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
* Return: position >= 0 on success
* -ENXIO on failure
*/
-static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
+static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled,
+ struct range *hpa_range)
{
struct cxl_port *iter, *port = cxled_to_port(cxled);
struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
- struct range *range = &cxled->cxld.hpa_range;
int parent_ways = 0, parent_pos = 0, pos = 0;
int rc;
@@ -1932,7 +1933,8 @@ static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
if (is_cxl_root(iter))
break;
- rc = find_pos_and_ways(iter, range, &parent_pos, &parent_ways);
+ rc = find_pos_and_ways(iter, hpa_range, &parent_pos,
+ &parent_ways);
if (rc)
return rc;
@@ -1942,7 +1944,7 @@ static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
dev_dbg(&cxlmd->dev,
"decoder:%s parent:%s port:%s range:%#llx-%#llx pos:%d\n",
dev_name(&cxled->cxld.dev), dev_name(cxlmd->dev.parent),
- dev_name(&port->dev), range->start, range->end, pos);
+ dev_name(&port->dev), hpa_range->start, hpa_range->end, pos);
return pos;
}
@@ -1955,7 +1957,7 @@ static int cxl_region_sort_targets(struct cxl_region *cxlr)
for (i = 0; i < p->nr_targets; i++) {
struct cxl_endpoint_decoder *cxled = p->targets[i];
- cxled->pos = cxl_calc_interleave_pos(cxled);
+ cxled->pos = cxl_calc_interleave_pos(cxled, &cxlr->hpa_range);
/*
* Record that sorting failed, but still continue to calc
* cxled->pos so that follow-on code paths can reliably
@@ -2139,7 +2141,7 @@ static int cxl_region_attach(struct cxl_region *cxlr,
struct cxl_endpoint_decoder *cxled = p->targets[i];
int test_pos;
- test_pos = cxl_calc_interleave_pos(cxled);
+ test_pos = cxl_calc_interleave_pos(cxled, &cxlr->hpa_range);
dev_dbg(&cxled->cxld.dev,
"Test cxl_calc_interleave_pos(): %s test_pos:%d cxled->pos:%d\n",
(test_pos == cxled->pos) ? "success" : "fail",
--
2.47.3
next prev parent reply other threads:[~2026-01-10 11:47 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-10 11:46 [PATCH v9 00/13] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2026-01-10 11:46 ` [PATCH v9 01/13] cxl/region: Rename misleading variable name @hpa to @hpa_range Robert Richter
2026-01-14 3:12 ` Alison Schofield
2026-01-10 11:46 ` [PATCH v9 02/13] cxl/region: Store root decoder in struct cxl_region Robert Richter
2026-01-14 3:13 ` Alison Schofield
2026-01-10 11:46 ` [PATCH v9 03/13] cxl/region: Store HPA range " Robert Richter
2026-01-14 3:14 ` Alison Schofield
2026-01-10 11:46 ` [PATCH v9 04/13] cxl: Simplify cxl_root_ops allocation and handling Robert Richter
2026-01-14 3:16 ` Alison Schofield
2026-01-10 11:46 ` [PATCH v9 05/13] cxl/region: Separate region parameter setup and region construction Robert Richter
2026-01-14 3:17 ` Alison Schofield
2026-01-10 11:46 ` Robert Richter [this message]
2026-01-14 3:17 ` [PATCH v9 06/13] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() Alison Schofield
2026-01-10 11:46 ` [PATCH v9 07/13] cxl/region: Use region data to get the root decoder Robert Richter
2026-01-14 3:19 ` Alison Schofield
2026-01-10 11:46 ` [PATCH v9 08/13] cxl: Introduce callback for HPA address ranges translation Robert Richter
2026-01-14 3:20 ` Alison Schofield
2026-01-10 11:46 ` [PATCH v9 09/13] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2026-01-10 11:46 ` [PATCH v9 10/13] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2026-01-14 7:47 ` Ard Biesheuvel
2026-01-14 14:00 ` Robert Richter
2026-01-14 15:21 ` Ard Biesheuvel
2026-01-14 18:08 ` Jonathan Cameron
2026-01-15 8:04 ` Peter Zijlstra
2026-01-15 8:30 ` Ard Biesheuvel
2026-01-16 14:38 ` Peter Zijlstra
2026-01-19 14:33 ` Robert Richter
2026-01-19 15:00 ` Gregory Price
2026-01-19 15:15 ` Dave Jiang
2026-01-19 16:03 ` Yazen Ghannam
2026-01-21 0:35 ` dan.j.williams
2026-01-21 14:58 ` Yazen Ghannam
2026-01-21 22:09 ` dan.j.williams
2026-01-21 23:12 ` Gregory Price
2026-01-22 2:05 ` dan.j.williams
2026-01-22 6:09 ` dan.j.williams
2026-01-20 21:23 ` dan.j.williams
2026-01-10 11:46 ` [PATCH v9 11/13] cxl/atl: Lock decoders that need address translation Robert Richter
2026-01-10 11:46 ` [PATCH v9 12/13] cxl/region: Factor out code into cxl_region_setup_poison() Robert Richter
2026-01-13 22:39 ` Dave Jiang
2026-01-14 3:32 ` Alison Schofield
2026-01-14 18:17 ` Jonathan Cameron
2026-01-10 11:46 ` [PATCH v9 13/13] cxl: Disable HPA/SPA translation handlers for Normalized Addressing Robert Richter
2026-01-13 23:15 ` Dave Jiang
2026-01-14 3:59 ` Alison Schofield
2026-01-14 11:32 ` Robert Richter
2026-01-14 18:22 ` Jonathan Cameron
2026-02-03 18:52 ` [PATCH v9 00/13] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Dave Jiang
2026-02-03 21:35 ` Gregory Price
2026-02-04 12:58 ` Robert Richter
2026-02-04 17:56 ` Dave Jiang
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