From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <dave@stgolabs.net>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <shiju.jose@huawei.com>,
<ming.li@zohomail.com>, <Smita.KoralahalliChannabasappa@amd.com>,
<rrichter@amd.com>, <dan.carpenter@linaro.org>,
<PradeepVineshReddy.Kodamati@amd.com>, <lukas@wunner.de>,
<Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <vishal.l.verma@intel.com>,
<alucerop@amd.com>, <ira.weiny@intel.com>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v14 19/34] cxl/port: Fix devm resource leaks around with dport management
Date: Thu, 15 Jan 2026 14:46:05 +0000 [thread overview]
Message-ID: <20260115144605.00000666@huawei.com> (raw)
In-Reply-To: <20260114182055.46029-20-terry.bowman@amd.com>
On Wed, 14 Jan 2026 12:20:40 -0600
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Dan Williams <dan.j.williams@intel.com>
>
> With dport addition moving out of cxl_switch_port_probe() it is no longer
> the case that a single dport-add failure will cause all dport resources
> to be automatically unwound.
>
> devm still helps all dport resources get cleaned up when the port is
> detached, but setup now needs to avoid leaking resources if an early exit
> occurs during setup.
>
> Convert from a "devm add" model, to an "auto remove" model that makes the
> caller responsible for registering devm reclaim after the object is fully
> instantiated.
>
> As a side of effect of this reorganization port->nr_dports is now always
> consistent with the number of entries in the port->dports xarray, and this
> can stop playing games with ida_is_empty() which is unreliable as a
> detector of whether decoders are setup. I.e. consider how
> CONFIG_DEBUG_KOBJECT_RELEASE might wreak havoc with this approach.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Terry Bowman <terry.bowman@amd.com>
>
> ---
>
> Changes in v13 -> v14:
> - New patch
Hi Dan, Terry,
I think this needs a little reorganization to ensure we don't have
dport and dport_add both being the same pointer for different free
reasons. Adding a helper and we can combine them with a clear
hand over of ownership.
Wrapping devres_remove_group() in a function that is called close_group()
rings alarm bells.
Jonathan
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index fef3aa0c6680..a05a1812bb6e 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> -static struct cxl_dport *
> -__devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
> - int port_id, resource_size_t component_reg_phys,
> - resource_size_t rcrb)
> +static struct cxl_dport *__cxl_add_dport(struct cxl_port *port,
> + struct device *dport_dev, int port_id,
> + resource_size_t component_reg_phys,
> + resource_size_t rcrb)
> {
> char link_name[CXL_TARGET_STRLEN];
> - struct cxl_dport *dport;
> - struct device *host;
> int rc;
>
> - if (is_cxl_root(port))
> - host = port->uport_dev;
> - else
> - host = &port->dev;
> -
> - if (!host->driver) {
> - dev_WARN_ONCE(&port->dev, 1, "dport:%s bad devm context\n",
> - dev_name(dport_dev));
> - return ERR_PTR(-ENXIO);
> - }
> -
> if (snprintf(link_name, CXL_TARGET_STRLEN, "dport%d", port_id) >=
> CXL_TARGET_STRLEN)
> return ERR_PTR(-EINVAL);
>
> - dport = devm_kzalloc(host, sizeof(*dport), GFP_KERNEL);
> + struct cxl_dport *dport __free(kfree) =
> + kzalloc(sizeof(*dport), GFP_KERNEL);
> if (!dport)
> return ERR_PTR(-ENOMEM);
>
> @@ -1176,48 +1175,27 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
> &component_reg_phys);
>
> cond_cxl_root_lock(port);
> - rc = add_dport(port, dport);
> + struct cxl_dport *dport_add __free(remove_dport) =
> + add_dport(port, dport);
This pattern of having both dport and dport_add effectively
pointing to the same pointer concerns me from a readability / maintainability
point of view. We've often made use of helper functions to avoid doing
this and I think that would make sense here as well.
Take everything down to and including dport_add() as a helper called
something like (naming needs work!)
struct dport_dev *dport __free(remove_and_free_dport) =
add_dport_wrapper();
With the __free doing the kfree as well as remove.
> cond_cxl_root_unlock(port);
> - if (rc)
> - return ERR_PTR(rc);
> -
> - /*
> - * Setup port register if this is the first dport showed up. Having
> - * a dport also means that there is at least 1 active link.
> - */
> - if (port->nr_dports == 1 &&
> - port->component_reg_phys != CXL_RESOURCE_NONE) {
> - rc = cxl_port_setup_regs(port, port->component_reg_phys);
> - if (rc) {
> - xa_erase(&port->dports, (unsigned long)dport->dport_dev);
> - return ERR_PTR(rc);
> - }
> - port->component_reg_phys = CXL_RESOURCE_NONE;
> - }
> + if (IS_ERR(dport_add))
> + return dport_add;
>
> - get_device(dport_dev);
> - rc = devm_add_action_or_reset(host, cxl_dport_remove, dport);
> - if (rc)
> - return ERR_PTR(rc);
> + if (dev_is_pci(dport_dev))
> + dport->link_latency = cxl_pci_get_latency(to_pci_dev(dport_dev));
>
> rc = sysfs_create_link(&port->dev.kobj, &dport_dev->kobj, link_name);
> if (rc)
> return ERR_PTR(rc);
>
> - rc = devm_add_action_or_reset(host, cxl_dport_unlink, dport);
> - if (rc)
> - return ERR_PTR(rc);
> -
> - if (dev_is_pci(dport_dev))
> - dport->link_latency = cxl_pci_get_latency(to_pci_dev(dport_dev));
> -
> cxl_debugfs_create_dport_dir(dport);
>
> - return dport;
> + retain_and_null_ptr(dport_add);
> + return no_free_ptr(dport);
> }
> +
> +/*
> + * Note: this only services dynamic removal of mid-level ports, root ports are
> + * always removed by the platform driver (e.g. cxl_acpi). @host can be
> + * hard-coded to &port->dev.
> + */
> static void del_dport(struct cxl_dport *dport)
> {
> struct cxl_port *port = dport->port;
>
> - devm_release_action(&port->dev, cxl_dport_unlink, dport);
> - devm_release_action(&port->dev, cxl_dport_remove, dport);
> - devm_kfree(&port->dev, dport);
> + devm_release_action(&port->dev, unlink_dport, dport);
> }
>
> static void del_dports(struct cxl_port *port)
> @@ -1597,10 +1603,24 @@ static int update_decoder_targets(struct device *dev, void *data)
> return 0;
> }
>
> -DEFINE_FREE(del_cxl_dport, struct cxl_dport *, if (!IS_ERR_OR_NULL(_T)) del_dport(_T))
> +static struct cxl_port *cxl_port_devres_group(struct cxl_port *port)
> +{
> + if (!devres_open_group(&port->dev, port, GFP_KERNEL))
> + return ERR_PTR(-ENOMEM);
> + return port;
> +}
> +DEFINE_FREE(cxl_port_group_free, struct cxl_port *,
> + if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T))
> +
> +static void cxl_port_group_close(struct cxl_port *port)
This feels like misleading naming and I'm not sure what intent is.
Would have expected it to call devres_close_group()
> +{
> + devres_remove_group(&port->dev, port);
> +}
> +
> static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
> struct device *dport_dev)
> {
> + struct cxl_dport *new_dport;
> struct cxl_dport *dport;
> int rc;
>
> @@ -1615,29 +1635,46 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
> return ERR_PTR(-EBUSY);
> }
>
> - struct cxl_dport *new_dport __free(del_cxl_dport) =
> - devm_cxl_add_dport_by_dev(port, dport_dev);
> - if (IS_ERR(new_dport))
> - return new_dport;
> -
> - cxl_switch_parse_cdat(new_dport);
> + /*
> + * With the first dport arrival it is now safe to start looking at
> + * component registers. Be careful to not strand resources if dport
> + * creation ultimately fails.
> + */
> + struct cxl_port *port_group __free(cxl_port_group_free) =
> + cxl_port_devres_group(port);
> + if (IS_ERR(port_group))
> + return ERR_CAST(port_group);
>
> - if (ida_is_empty(&port->decoder_ida)) {
> + if (port->nr_dports == 0) {
> rc = devm_cxl_switch_port_decoders_setup(port);
> if (rc)
> return ERR_PTR(rc);
> - dev_dbg(&port->dev, "first dport%d:%s added with decoders\n",
> - new_dport->port_id, dev_name(dport_dev));
> - return no_free_ptr(new_dport);
> + /*
> + * Note, when nr_dports returns to zero the port is unregistered
> + * and triggers cleanup. I.e. no need for open-coded release
> + * action on dport removal. See cxl_detach_ep() for that logic.
> + */
> }
>
> + new_dport = cxl_add_dport_by_dev(port, dport_dev);
> + if (IS_ERR(new_dport))
> + return new_dport;
> +
> + rc = cxl_dport_autoremove(new_dport);
> + if (rc)
> + return ERR_PTR(rc);
> +
> + cxl_switch_parse_cdat(new_dport);
> +
> + cxl_port_group_close(no_free_ptr(port_group));
Give name vs what it does I'm not sure how this currently works.
> +
> + dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n",
> + port->nr_dports - 1, new_dport->port_id, dev_name(dport_dev));
> +
> /* New dport added, update the decoder targets */
> device_for_each_child(&port->dev, new_dport, update_decoder_targets);
>
> - dev_dbg(&port->dev, "dport%d:%s added\n", new_dport->port_id,
> - dev_name(dport_dev));
> -
> - return no_free_ptr(new_dport);
> + return new_dport;
> }
>
> static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev,
next prev parent reply other threads:[~2026-01-15 14:46 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-14 18:20 [PATCH v14 00/34] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-01-14 18:20 ` [PATCH v14 01/34] PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2026-01-22 18:58 ` Bjorn Helgaas
2026-01-22 19:43 ` Bowman, Terry
2026-01-14 18:20 ` [PATCH v14 02/34] PCI: Update CXL DVSEC definitions Terry Bowman
2026-01-14 18:53 ` Jonathan Cameron
2026-01-19 23:44 ` dan.j.williams
2026-01-22 18:37 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 03/34] PCI: Introduce pcie_is_cxl() Terry Bowman
2026-01-21 1:19 ` dan.j.williams
2026-01-22 18:39 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 04/34] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2026-01-14 18:20 ` [PATCH v14 05/34] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2026-01-14 18:20 ` [PATCH v14 06/34] PCI: Replace cxl_error_is_native() with pcie_aer_is_native() Terry Bowman
2026-01-14 18:55 ` Jonathan Cameron
2026-01-14 20:16 ` Dave Jiang
2026-01-14 20:15 ` Dave Jiang
2026-01-22 18:23 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 07/34] cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Terry Bowman
2026-01-14 20:51 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 08/34] cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c Terry Bowman
2026-01-14 20:35 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 09/34] PCI/AER: Export pci_aer_unmask_internal_errors() Terry Bowman
2026-01-14 19:01 ` Jonathan Cameron
2026-01-14 19:09 ` Kuppuswamy Sathyanarayanan
2026-01-14 20:40 ` Dave Jiang
2026-01-20 2:09 ` dan.j.williams
2026-01-22 10:31 ` Lukas Wunner
2026-01-22 16:48 ` dan.j.williams
2026-01-22 18:51 ` Lukas Wunner
2026-01-22 18:49 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 10/34] PCI/AER: Update is_internal_error() to be non-static is_aer_internal_error() Terry Bowman
2026-01-14 19:08 ` Jonathan Cameron
2026-01-15 20:42 ` dan.j.williams
2026-01-22 13:34 ` Lukas Wunner
2026-01-22 19:09 ` dan.j.williams
2026-01-22 19:32 ` Lukas Wunner
2026-01-22 21:32 ` dan.j.williams
2026-01-23 12:22 ` Jonathan Cameron
2026-01-20 2:20 ` dan.j.williams
2026-01-20 15:15 ` Bowman, Terry
2026-01-20 16:53 ` dan.j.williams
2026-01-22 18:48 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 11/34] PCI/AER: Move CXL RCH error handling to aer_cxl_rch.c Terry Bowman
2026-01-22 17:23 ` Markus Elfring
2026-01-22 20:05 ` Bowman, Terry
2026-01-22 18:53 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 12/34] PCI/AER: Use guard() in cxl_rch_handle_error_iter() Terry Bowman
2026-01-14 19:11 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 13/34] PCI/AER: Replace PCIEAER_CXL symbol with CXL_RAS Terry Bowman
2026-01-14 19:12 ` Jonathan Cameron
2026-01-14 20:49 ` Dave Jiang
2026-01-14 20:50 ` Dave Jiang
2026-01-22 18:24 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 14/34] PCI/AER: Report CXL or PCIe bus type in AER trace logging Terry Bowman
2026-01-14 19:45 ` Jonathan Cameron
2026-01-15 15:55 ` Mauro Carvalho Chehab
2026-01-14 20:56 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 15/34] PCI/AER: Update struct aer_err_info with kernel-doc formatting Terry Bowman
2026-01-14 19:48 ` Jonathan Cameron
2026-01-15 20:56 ` dan.j.williams
2026-01-14 21:06 ` Dave Jiang
2026-01-22 18:29 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 16/34] cxl/mem: Clarify @host for devm_cxl_add_nvdimm() Terry Bowman
2026-01-14 19:49 ` Jonathan Cameron
2026-01-14 21:08 ` Dave Jiang
2026-01-16 3:07 ` dan.j.williams
2026-01-16 16:22 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 17/34] cxl: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2026-01-14 18:20 ` [PATCH v14 18/34] cxl/port: Remove "enumerate dports" helpers Terry Bowman
2026-01-14 19:50 ` Jonathan Cameron
2026-01-14 21:23 ` Dave Jiang
2026-01-16 3:15 ` dan.j.williams
2026-01-14 21:24 ` Dave Jiang
2026-01-16 3:21 ` dan.j.williams
2026-01-14 18:20 ` [PATCH v14 19/34] cxl/port: Fix devm resource leaks around with dport management Terry Bowman
2026-01-14 21:26 ` Dave Jiang
2026-01-15 14:46 ` Jonathan Cameron [this message]
2026-01-16 4:45 ` dan.j.williams
2026-01-16 15:01 ` Jonathan Cameron
2026-01-16 16:16 ` Jonathan Cameron
2026-01-19 23:02 ` dan.j.williams
2026-01-20 12:25 ` Jonathan Cameron
2026-01-19 2:48 ` dan.j.williams
2026-01-14 18:20 ` [PATCH v14 20/34] cxl/port: Move dport operations to a driver event Terry Bowman
2026-01-14 21:45 ` Dave Jiang
2026-01-15 14:56 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 21/34] cxl/port: Move dport RAS reporting to a port resource Terry Bowman
2026-01-14 21:47 ` Dave Jiang
2026-01-15 15:02 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 22/34] cxl: Update CXL Endpoint tracing Terry Bowman
2026-01-14 18:20 ` [PATCH v14 23/34] cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2026-01-14 21:53 ` Dave Jiang
2026-01-15 15:17 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 24/34] cxl/port: Move endpoint component register management to cxl_port Terry Bowman
2026-01-14 21:55 ` Dave Jiang
2026-01-15 15:28 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 25/34] cxl/port: Map Port component registers before switchport init Terry Bowman
2026-01-14 21:59 ` Dave Jiang
2026-01-15 15:30 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 26/34] cxl: Change CXL handlers to use guard() instead of scoped_guard() Terry Bowman
2026-01-23 10:05 ` Markus Elfring
2026-01-14 18:20 ` [PATCH v14 27/34] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-01-14 18:58 ` Kuppuswamy Sathyanarayanan
2026-01-14 19:20 ` Bowman, Terry
2026-01-14 19:45 ` Kuppuswamy Sathyanarayanan
2026-01-14 18:20 ` [PATCH v14 28/34] PCI/AER: Move AER driver's CXL VH handling to pcie/aer_cxl_vh.c Terry Bowman
2026-01-15 15:40 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 29/34] cxl/port: Unify endpoint and switch port lookup Terry Bowman
2026-01-14 23:04 ` Dave Jiang
2026-01-15 15:44 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 30/34] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2026-01-14 23:18 ` Dave Jiang
2026-01-16 14:42 ` Bowman, Terry
2026-01-15 16:01 ` Jonathan Cameron
2026-01-15 17:29 ` Bowman, Terry
2026-01-22 18:32 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 31/34] PCI: Introduce CXL Port protocol error handlers Terry Bowman
2026-01-14 23:37 ` Dave Jiang
2026-01-15 16:12 ` Jonathan Cameron
2026-01-22 18:27 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 32/34] cxl: Update Endpoint uncorrectable protocol error handling Terry Bowman
2026-01-14 22:07 ` dan.j.williams
2026-01-15 15:26 ` Bowman, Terry
2026-01-15 15:27 ` Bowman, Terry
2026-01-14 18:20 ` [PATCH v14 33/34] cxl: Update Endpoint correctable " Terry Bowman
2026-01-14 18:20 ` [PATCH v14 34/34] cxl: Enable CXL protocol errors during CXL Port probe Terry Bowman
2026-01-15 16:18 ` Jonathan Cameron
2026-01-15 19:41 ` Bowman, Terry
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