Re: [PATCH v14 23/34] cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Wed, 14 Jan 2026 12:20:44 -0600
Terry Bowman <terry.bowman@amd.com> wrote:

> In preparation for CXL VH (Virtual Host) topology protocol error handling,
> add RAS capability registered mapping for all ports in a CXL VH topology.
> This includes the RAS capabilities of Switch Upstream Ports, Switch
> Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports
> ("downstream")
> 
> Update cxl_port_add_dport() to map the upstream RAS capability on first
> 'dport' attach, and downstream RAS capability on each 'dport' attach.
> Arrange for dport mappings to be released at del_dport() time.
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> [djbw: reword changelog, fix devm handling]
> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> 
One comment inline on which level we handle failures in ras setup at but
that's already true so things aren't made worse by this.

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

I'm not particularly keen on failing to pass errors up to
callers of devm_cxl_dport_ras_setup() which could then cleanly
ignore them with comments saying why. However, that predates this
anyway so a question for another day.