* [PATCH v3 01/12] dt-bindings: document access-controllers property for coresight peripherals
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 02/12] dt-bindings: pinctrl: document access-controllers property for stm32 HDP Gatien Chevallier
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Document the access-controllers for coresight peripherals in case some
access checks need to be performed to use them.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml | 3 +++
.../devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml | 3 +++
Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml | 3 +++
Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml | 3 +++
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml | 3 +++
Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml | 3 +++
6 files changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
index 2a91670ccb8c..949444aba1f8 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
@@ -128,6 +128,9 @@ properties:
"#address-cells":
const: 1
+ access-controllers:
+ maxItems: 1
+
patternProperties:
'^trig-conns@([0-9]+)$':
type: object
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
index b74db15e5f8a..b0693cd46d27 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
@@ -78,6 +78,9 @@ properties:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
+ access-controllers:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
index 71f2e1ed27e5..10ebbbeadf93 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
@@ -118,6 +118,9 @@ properties:
description: Output connection from the ETM to CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
+ access-controllers:
+ maxItems: 1
+
required:
- compatible
- clocks
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
index 378380c3f5aa..f243e76f597f 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
@@ -73,6 +73,9 @@ properties:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
+ access-controllers:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
index 96dd5b5f771a..9dc096698c65 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
@@ -128,6 +128,9 @@ properties:
- const: tracedata
- const: metadata
+ access-controllers:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
index a207f6899e67..29bbc3961fdf 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
@@ -70,6 +70,9 @@ properties:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
+ access-controllers:
+ maxItems: 1
+
required:
- compatible
- reg
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 02/12] dt-bindings: pinctrl: document access-controllers property for stm32 HDP
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 01/12] dt-bindings: document access-controllers property for coresight peripherals Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-27 9:20 ` Linus Walleij
2026-01-21 12:34 ` [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus Gatien Chevallier
` (9 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
HDP being functional depends on the debug configuration on the platform
that can be checked using the access-controllers property, document it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
index 845b6b7b7552..8f8b4b68aaa3 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
@@ -27,6 +27,12 @@ properties:
clocks:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ items:
+ - description: debug configuration access controller
+ - description: access controller that manages the HDP as a peripheral
+
patternProperties:
"^hdp[0-7]-pins$":
type: object
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 02/12] dt-bindings: pinctrl: document access-controllers property for stm32 HDP
2026-01-21 12:34 ` [PATCH v3 02/12] dt-bindings: pinctrl: document access-controllers property for stm32 HDP Gatien Chevallier
@ 2026-01-27 9:20 ` Linus Walleij
0 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2026-01-27 9:20 UTC (permalink / raw)
To: Gatien Chevallier
Cc: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Maxime Coquelin, Alexandre Torgue,
jens.wiklander, coresight, linux-arm-kernel, devicetree,
linux-kernel, linux-gpio, linux-stm32
On Wed, Jan 21, 2026 at 1:35 PM Gatien Chevallier
<gatien.chevallier@foss.st.com> wrote:
> HDP being functional depends on the debug configuration on the platform
> that can be checked using the access-controllers property, document it.
>
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 01/12] dt-bindings: document access-controllers property for coresight peripherals Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 02/12] dt-bindings: pinctrl: document access-controllers property for stm32 HDP Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 15:21 ` Rob Herring
2026-01-21 12:34 ` [PATCH v3 04/12] bus: stm32_firewall: allow check on different firewall controllers Gatien Chevallier
` (8 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Document the stm32 debug bus. The debug bus is responsible for
checking the debug sub-system accessibility before probing any related
drivers.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
.../bindings/bus/st,stm32mp131-dbg-bus.yaml | 79 ++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
new file mode 100644
index 000000000000..2db35e41e76c
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Coresight bus
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+description:
+ The STM32 debug bus is in charge of checking the debug configuration
+ of the platform before probing the peripheral drivers that rely on the debug
+ domain.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - st,stm32mp131-dbg-bus
+ - st,stm32mp151-dbg-bus
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ reg:
+ maxItems: 1
+
+ "#access-controller-cells":
+ const: 1
+ description:
+ Contains the debug profile necessary to access the peripheral.
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Debug related peripherals
+ type: object
+
+ additionalProperties: true
+
+ required:
+ - access-controllers
+
+required:
+ - "#access-controller-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - ranges
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+
+ dbg_bus: bus@50080000 {
+ compatible = "st,stm32mp131-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+
+ cs_cti_trace: cti@50094000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ };
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus
2026-01-21 12:34 ` [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus Gatien Chevallier
@ 2026-01-21 15:21 ` Rob Herring
2026-01-22 14:13 ` Gatien CHEVALLIER
0 siblings, 1 reply; 16+ messages in thread
From: Rob Herring @ 2026-01-21 15:21 UTC (permalink / raw)
To: Gatien Chevallier
Cc: Suzuki K Poulose, Mike Leach, James Clark, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, Leo Yan, Clément Le Goffic,
Linus Walleij, Maxime Coquelin, Alexandre Torgue, jens.wiklander,
coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32
On Wed, Jan 21, 2026 at 01:34:37PM +0100, Gatien Chevallier wrote:
> Document the stm32 debug bus. The debug bus is responsible for
> checking the debug sub-system accessibility before probing any related
> drivers.
>
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 79 ++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
> new file mode 100644
> index 000000000000..2db35e41e76c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STM32 Coresight bus
> +
> +maintainers:
> + - Gatien Chevallier <gatien.chevallier@foss.st.com>
> +
> +description:
> + The STM32 debug bus is in charge of checking the debug configuration
> + of the platform before probing the peripheral drivers that rely on the debug
> + domain.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - st,stm32mp131-dbg-bus
> + - st,stm32mp151-dbg-bus
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> + reg:
> + maxItems: 1
> +
> + "#access-controller-cells":
> + const: 1
> + description:
> + Contains the debug profile necessary to access the peripheral.
> +
> +patternProperties:
> + "^.*@[0-9a-f]+$":
> + description: Debug related peripherals
> + type: object
> +
> + additionalProperties: true
> +
> + required:
> + - access-controllers
> +
> +required:
> + - "#access-controller-cells"
> + - "#address-cells"
> + - "#size-cells"
> + - compatible
> + - ranges
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/stm32mp1-clks.h>
> +
> + dbg_bus: bus@50080000 {
> + compatible = "st,stm32mp131-dbg-bus";
> + reg = <0x50080000 0x3f80000>;
That's a lot of registers... Yet the bus driver doesn't access any.
Looks to me like this belongs in ranges instead if there aren't any bus
registers. Or its size should be just the registers and then the whole
region size goes in ranges.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #access-controller-cells = <1>;
> + ranges;
> +
> + cs_cti_trace: cti@50094000 {
> + compatible = "arm,coresight-cti", "arm,primecell";
> + reg = <0x50094000 0x1000>;
> + clocks = <&rcc CK_DBG>;
> + clock-names = "apb_pclk";
> + access-controllers = <&dbg_bus 0>;
> + };
> + };
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus
2026-01-21 15:21 ` Rob Herring
@ 2026-01-22 14:13 ` Gatien CHEVALLIER
0 siblings, 0 replies; 16+ messages in thread
From: Gatien CHEVALLIER @ 2026-01-22 14:13 UTC (permalink / raw)
To: Rob Herring
Cc: Suzuki K Poulose, Mike Leach, James Clark, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, Leo Yan, Clément Le Goffic,
Linus Walleij, Maxime Coquelin, Alexandre Torgue, jens.wiklander,
coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32
On 1/21/26 16:21, Rob Herring wrote:
> On Wed, Jan 21, 2026 at 01:34:37PM +0100, Gatien Chevallier wrote:
>> Document the stm32 debug bus. The debug bus is responsible for
>> checking the debug sub-system accessibility before probing any related
>> drivers.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> ---
>> .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 79 ++++++++++++++++++++++
>> 1 file changed, 79 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
>> new file mode 100644
>> index 000000000000..2db35e41e76c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
>> @@ -0,0 +1,79 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32 Coresight bus
>> +
>> +maintainers:
>> + - Gatien Chevallier <gatien.chevallier@foss.st.com>
>> +
>> +description:
>> + The STM32 debug bus is in charge of checking the debug configuration
>> + of the platform before probing the peripheral drivers that rely on the debug
>> + domain.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - st,stm32mp131-dbg-bus
>> + - st,stm32mp151-dbg-bus
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 1
>> +
>> + ranges: true
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + "#access-controller-cells":
>> + const: 1
>> + description:
>> + Contains the debug profile necessary to access the peripheral.
>> +
>> +patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + description: Debug related peripherals
>> + type: object
>> +
>> + additionalProperties: true
>> +
>> + required:
>> + - access-controllers
>> +
>> +required:
>> + - "#access-controller-cells"
>> + - "#address-cells"
>> + - "#size-cells"
>> + - compatible
>> + - ranges
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/stm32mp1-clks.h>
>> +
>> + dbg_bus: bus@50080000 {
>> + compatible = "st,stm32mp131-dbg-bus";
>> + reg = <0x50080000 0x3f80000>;
>
> That's a lot of registers... Yet the bus driver doesn't access any.
> Looks to me like this belongs in ranges instead if there aren't any bus
> registers. Or its size should be just the registers and then the whole
> region size goes in ranges.
>
Hello Rob,
Understandable comment. I'll switch to defining the range in the
ranges property in the V3.
Thank you,
Gatien
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #access-controller-cells = <1>;
>> + ranges;
>> +
>> + cs_cti_trace: cti@50094000 {
>> + compatible = "arm,coresight-cti", "arm,primecell";
>> + reg = <0x50094000 0x1000>;
>> + clocks = <&rcc CK_DBG>;
>> + clock-names = "apb_pclk";
>> + access-controllers = <&dbg_bus 0>;
>> + };
>> + };
>>
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 04/12] bus: stm32_firewall: allow check on different firewall controllers
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (2 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 05/12] bus: stm32_firewall: add stm32_firewall_get_grant_all_access() API Gatien Chevallier
` (7 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Current implementation restricts the check on the firewall controller
being the bus parent. Change this by using the controller referenced
in each firewall queries.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
drivers/bus/stm32_firewall.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c
index 2fc9761dadec..2717754d811d 100644
--- a/drivers/bus/stm32_firewall.c
+++ b/drivers/bus/stm32_firewall.c
@@ -274,7 +274,7 @@ int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_contr
}
for (i = 0; i < len; i++) {
- if (firewall_controller->grant_access(firewall_controller,
+ if (firewall_controller->grant_access(firewalls[i].firewall_ctrl,
firewalls[i].firewall_id)) {
/*
* Peripheral access not allowed or not defined.
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 05/12] bus: stm32_firewall: add stm32_firewall_get_grant_all_access() API
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (3 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 04/12] bus: stm32_firewall: allow check on different firewall controllers Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 06/12] drivers: bus: add the stm32 debug bus driver Gatien Chevallier
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Add the stm32_firewall_get_grant_all_access() API to be able to fetch
all firewall references in an access-controllers property and try to grant
access to all of them.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
drivers/bus/stm32_firewall.c | 42 +++++++++++++++++++++++++++++++
include/linux/bus/stm32_firewall_device.h | 26 +++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c
index 2717754d811d..c9e6299197c3 100644
--- a/drivers/bus/stm32_firewall.c
+++ b/drivers/bus/stm32_firewall.c
@@ -185,6 +185,48 @@ void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 su
}
EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+int stm32_firewall_get_grant_all_access(struct device *dev, struct stm32_firewall **firewall,
+ int *nb_firewall)
+{
+ struct stm32_firewall *loc_firewall;
+ int err;
+ int i;
+
+ *nb_firewall = of_count_phandle_with_args(dev->of_node, "access-controllers",
+ "#access-controller-cells");
+ if (*nb_firewall < 0)
+ return *nb_firewall;
+
+ if (!*nb_firewall) {
+ *firewall = NULL;
+ return 0;
+ }
+
+ loc_firewall = devm_kcalloc(dev, *nb_firewall, sizeof(*loc_firewall), GFP_KERNEL);
+ if (!loc_firewall)
+ return -ENOMEM;
+
+ /* Get stm32 firewall information */
+ err = stm32_firewall_get_firewall(dev->of_node, loc_firewall, *nb_firewall);
+ if (err)
+ return err;
+
+ for (i = 0; i < *nb_firewall; i++) {
+ err = stm32_firewall_grant_access(&loc_firewall[i]);
+ if (err) {
+ while (i--)
+ stm32_firewall_release_access(&loc_firewall[i]);
+
+ return err;
+ }
+ }
+
+ *firewall = loc_firewall;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_get_grant_all_access);
+
/* Firewall controller API */
int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller)
diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h
index eaa7a3f54450..6c878f3ca86f 100644
--- a/include/linux/bus/stm32_firewall_device.h
+++ b/include/linux/bus/stm32_firewall_device.h
@@ -112,6 +112,25 @@ int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsy
*/
void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+/**
+ * stm32_firewall_get_grant_all_access - Allocate and get all the firewall(s) associated to given
+ * device. Then, try to grant access rights for each element.
+ * This function is basically a helper function that wraps
+ * both stm32_firewall_get_firewall() and
+ * stm32_firewall_grant_access() on all firewall references of
+ * a device along with the allocation of the array.
+ * Realease access using stm32_firewall_release_access* APIs
+ * when done.
+ *
+ * @dev: Device performing the checks
+ * @firewall: Pointer to the array of firewall references to be allocated
+ * @nb_firewall: Number of allocated elements in @firewall
+ *
+ * Returns 0 on success, or appropriate errno code if error occurred.
+ */
+int stm32_firewall_get_grant_all_access(struct device *dev, struct stm32_firewall **firewall,
+ int *nb_firewall);
+
#else /* CONFIG_STM32_FIREWALL */
static inline int stm32_firewall_get_firewall(struct device_node *np,
@@ -141,5 +160,12 @@ static inline void stm32_firewall_release_access_by_id(struct stm32_firewall *fi
{
}
+static inline int stm32_firewall_get_grant_all_access(struct device *dev,
+ struct stm32_firewall **firewall,
+ int *nb_firewall)
+{
+ return -ENODEV;
+}
+
#endif /* CONFIG_STM32_FIREWALL */
#endif /* STM32_FIREWALL_DEVICE_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 06/12] drivers: bus: add the stm32 debug bus driver
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (4 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 05/12] bus: stm32_firewall: add stm32_firewall_get_grant_all_access() API Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 07/12] arm: dts: stm32: introduce the debug bus for stm32mp1x platforms Gatien Chevallier
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Add the stm32 debug bus driver that is responsible of checking the
debug subsystem accessibility before probing the related peripheral
drivers.
This driver is OP-TEE dependent and relies on the STM32 debug access
PTA.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
MAINTAINERS | 1 +
drivers/bus/Kconfig | 10 ++
drivers/bus/Makefile | 1 +
drivers/bus/stm32_dbg_bus.c | 236 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 248 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b11839cba9d..fd8390e02070 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24698,6 +24698,7 @@ F: drivers/power/supply/stc3117_fuel_gauge.c
ST STM32 FIREWALL
M: Gatien Chevallier <gatien.chevallier@foss.st.com>
S: Maintained
+F: drivers/bus/stm32_dbg_bus.c
F: drivers/bus/stm32_etzpc.c
F: drivers/bus/stm32_firewall.c
F: drivers/bus/stm32_rifsc.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index fe7600283e70..c9be21d5dfda 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -169,6 +169,16 @@ config QCOM_SSC_BLOCK_BUS
i2c/spi/uart controllers, a hexagon core, and a clock controller
which provides clocks for the above.
+config STM32_DBG_BUS
+ tristate "OP-TEE based debug access bus"
+ depends on OPTEE && STM32_FIREWALL
+ depends on ARCH_STM32 || COMPILE_TEST
+ help
+ Select this to get the support for the OP-TEE based STM32 debug bus
+ driver that is used to handle debug-related peripherals on STM32
+ platforms when the debug configuration is not accessible by the
+ normal world.
+
config STM32_FIREWALL
bool "STM32 Firewall framework"
depends on (ARCH_STM32 || COMPILE_TEST) && OF
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 8e693fe8a03a..799724cfc2df 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
+obj-$(CONFIG_STM32_DBG_BUS) += stm32_dbg_bus.o
obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o stm32_etzpc.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
diff --git a/drivers/bus/stm32_dbg_bus.c b/drivers/bus/stm32_dbg_bus.c
new file mode 100644
index 000000000000..9427d4da0da7
--- /dev/null
+++ b/drivers/bus/stm32_dbg_bus.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bus/stm32_firewall_device.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/tee_drv.h>
+#include <linux/types.h>
+
+#include "stm32_firewall.h"
+
+enum stm32_dbg_profile {
+ PERIPHERAL_DBG_PROFILE = 0,
+ HDP_DBG_PROFILE = 1,
+};
+
+enum stm32_dbg_pta_command {
+ /*
+ * PTA_CMD_GRANT_DBG_ACCESS - Verify the debug configuration against the given debug profile
+ * and grant access or not
+ *
+ * [in] value[0].a Debug profile to grant access to.
+ */
+ PTA_CMD_GRANT_DBG_ACCESS,
+};
+
+/**
+ * struct stm32_dbg_bus - OP-TEE based STM32 debug bus private data
+ * @dev: STM32 debug bus device.
+ * @ctx: OP-TEE context handler.
+ */
+struct stm32_dbg_bus {
+ struct device *dev;
+ struct tee_context *ctx;
+};
+
+/* Expect at most 1 instance of this driver */
+static struct stm32_dbg_bus *stm32_dbg_bus_priv;
+
+static int stm32_dbg_pta_open_session(u32 *id)
+{
+ struct tee_client_device *dbg_bus_dev = to_tee_client_device(stm32_dbg_bus_priv->dev);
+ struct tee_ioctl_open_session_arg sess_arg;
+ int ret;
+
+ memset(&sess_arg, 0, sizeof(sess_arg));
+ export_uuid(sess_arg.uuid, &dbg_bus_dev->id.uuid);
+ sess_arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL;
+
+ ret = tee_client_open_session(stm32_dbg_bus_priv->ctx, &sess_arg, NULL);
+ if (ret < 0 || sess_arg.ret) {
+ dev_err(stm32_dbg_bus_priv->dev, "Failed opening tee session, err: %#x\n",
+ sess_arg.ret);
+ return -EOPNOTSUPP;
+ }
+
+ *id = sess_arg.session;
+
+ return 0;
+}
+
+static void stm32_dbg_pta_close_session(u32 id)
+{
+ tee_client_close_session(stm32_dbg_bus_priv->ctx, id);
+}
+
+static int stm32_dbg_bus_grant_access(struct stm32_firewall_controller *ctrl, u32 dbg_profile)
+{
+ struct tee_ioctl_invoke_arg inv_arg = {0};
+ struct tee_param param[1] = {0};
+ u32 session_id;
+ int ret;
+
+ if (dbg_profile != PERIPHERAL_DBG_PROFILE && dbg_profile != HDP_DBG_PROFILE)
+ return -EOPNOTSUPP;
+
+ ret = stm32_dbg_pta_open_session(&session_id);
+ if (ret)
+ return ret;
+
+ inv_arg.func = PTA_CMD_GRANT_DBG_ACCESS;
+ inv_arg.session = session_id;
+ inv_arg.num_params = 1;
+ param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT;
+ param[0].u.value.a = dbg_profile;
+
+ ret = tee_client_invoke_func(stm32_dbg_bus_priv->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_dbg(stm32_dbg_bus_priv->dev,
+ "When invoking function, err %x, TEE returns: %x\n", ret, inv_arg.ret);
+ if (!ret)
+ ret = -EACCES;
+ }
+
+ stm32_dbg_pta_close_session(session_id);
+
+ return ret;
+}
+
+/* Implement mandatory release_access ops even if it does nothing*/
+static void stm32_dbg_bus_release_access(struct stm32_firewall_controller *ctrl, u32 dbg_profile)
+{
+}
+
+static int stm32_dbg_bus_plat_probe(struct platform_device *pdev)
+{
+ struct stm32_firewall_controller *dbg_controller;
+ int ret;
+
+ if (!stm32_dbg_bus_priv)
+ return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
+ "OP-TEE debug services not yet available\n");
+
+ dbg_controller = devm_kzalloc(&pdev->dev, sizeof(*dbg_controller), GFP_KERNEL);
+ if (!dbg_controller)
+ return dev_err_probe(&pdev->dev, -ENOMEM, "Couldn't allocate debug controller\n");
+
+ dbg_controller->dev = &pdev->dev;
+ dbg_controller->mmio = NULL;
+ dbg_controller->name = dev_driver_string(dbg_controller->dev);
+ dbg_controller->type = STM32_PERIPHERAL_FIREWALL;
+ dbg_controller->grant_access = stm32_dbg_bus_grant_access;
+ dbg_controller->release_access = stm32_dbg_bus_release_access;
+
+ ret = stm32_firewall_controller_register(dbg_controller);
+ if (ret) {
+ dev_err(dbg_controller->dev, "Couldn't register as a firewall controller: %d", ret);
+ return ret;
+ }
+
+ ret = stm32_firewall_populate_bus(dbg_controller);
+ if (ret) {
+ dev_err(dbg_controller->dev, "Couldn't populate debug bus: %d", ret);
+ stm32_firewall_controller_unregister(dbg_controller);
+ return ret;
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+ if (ret) {
+ dev_err(dbg_controller->dev, "Couldn't populate the node: %d", ret);
+ stm32_firewall_controller_unregister(dbg_controller);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id stm32_dbg_bus_of_match[] = {
+ { .compatible = "st,stm32mp131-dbg-bus", },
+ { .compatible = "st,stm32mp151-dbg-bus", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, stm32_dbg_bus_of_match);
+
+static struct platform_driver stm32_dbg_bus_driver = {
+ .probe = stm32_dbg_bus_plat_probe,
+ .driver = {
+ .name = "stm32-dbg-bus",
+ .of_match_table = stm32_dbg_bus_of_match,
+ },
+};
+
+static int optee_ctx_match(struct tee_ioctl_version_data *ver, const void *data)
+{
+ return (ver->impl_id == TEE_IMPL_ID_OPTEE);
+}
+
+static void stm32_dbg_bus_remove(struct tee_client_device *tee_dev)
+{
+ tee_client_close_context(stm32_dbg_bus_priv->ctx);
+ stm32_dbg_bus_priv = NULL;
+
+ of_platform_depopulate(&tee_dev->dev);
+}
+
+static int stm32_dbg_bus_probe(struct tee_client_device *tee_dev)
+{
+ struct device *dev = &tee_dev->dev;
+ struct stm32_dbg_bus *priv;
+ int ret = 0;
+
+ if (stm32_dbg_bus_priv)
+ return dev_err_probe(dev, -EBUSY,
+ "A STM32 debug bus device is already initialized\n");
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ /* Open context with TEE driver */
+ priv->ctx = tee_client_open_context(NULL, optee_ctx_match, NULL, NULL);
+ if (IS_ERR_OR_NULL(priv->ctx))
+ return dev_err_probe(dev, PTR_ERR_OR_ZERO(priv->ctx), "Cannot open TEE context\n");
+
+ stm32_dbg_bus_priv = priv;
+ stm32_dbg_bus_priv->dev = dev;
+
+ ret = platform_driver_register(&stm32_dbg_bus_driver);
+ if (ret) {
+ stm32_dbg_bus_remove(tee_dev);
+ return ret;
+ }
+
+ return ret;
+}
+
+static const struct tee_client_device_id optee_dbg_bus_id_table[] = {
+ {UUID_INIT(0xdd05bc8b, 0x9f3b, 0x49f0,
+ 0xb6, 0x49, 0x01, 0xaa, 0x10, 0xc1, 0xc2, 0x10)},
+ {}
+};
+
+static struct tee_client_driver stm32_optee_dbg_bus_driver = {
+ .id_table = optee_dbg_bus_id_table,
+ .probe = stm32_dbg_bus_probe,
+ .remove = stm32_dbg_bus_remove,
+ .driver = {
+ .name = "optee_dbg_bus",
+ },
+};
+
+module_tee_client_driver(stm32_optee_dbg_bus_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Gatien Chevallier <gatien.chevallier@foss.st.com>");
+MODULE_DESCRIPTION("OP-TEE based STM32 debug access bus driver");
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 07/12] arm: dts: stm32: introduce the debug bus for stm32mp1x platforms
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (5 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 06/12] drivers: bus: add the stm32 debug bus driver Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 08/12] arm: dts: stm32: enable the debug bus on stm32mp1x boards Gatien Chevallier
` (4 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier, Antonio Borneo
Some peripherals cannot be probed if a debug configuration is not set
in the BSEC.
Introduce a debug bus that will check the debug subsystem accessibility
before probing these peripheral drivers.
Add Coresight peripheral nodes under this bus and add the appropriate
access-controllers property to the HDP node.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm/boot/dts/st/stm32mp131.dtsi | 118 ++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp151.dtsi | 172 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp153.dtsi | 68 ++++++++++++++
3 files changed, 358 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index b9657ff91c23..315c2a952f60 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
@@ -964,9 +965,126 @@ hdp: pinctrl@5002a000 {
compatible = "st,stm32mp131-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
+ access-controllers = <&dbg_bus 1>;
status = "disabled";
};
+ dbg_bus: bus@50080000 {
+ compatible = "st,stm32mp131-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ cs_etf: etf@50092000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_tpiu: tpiu@50093000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cs_cti_trace: cti@50094000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+ };
+
+ cs_cti_cpu0: cti@500d8000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d8000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu0>;
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm0>;
+ };
+ };
+
+ cs_etm0: etm@500dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+ };
+
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index b1b568dfd126..1559263204be 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
@@ -274,9 +275,180 @@ hdp: pinctrl@5002a000 {
compatible = "st,stm32mp151-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
+ access-controllers = <&dbg_bus 1>;
status = "disabled";
};
+ dbg_bus: bus@50080000 {
+ compatible = "st,stm32mp151-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ cs_funnel: funnel@50091000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x50091000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ remote-endpoint = <&stm_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_etf: etf@50092000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_tpiu: tpiu@50093000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cs_cti_trace: cti@50094000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+ };
+
+ cs_stm: stm@500a0000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x500a0000 0x00001000>,
+ <0x90000000 0x01000000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ stm_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ cs_cti_cpu0: cti@500d8000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d8000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu0>;
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm0>;
+ };
+ };
+
+ cs_etm0: etm@500dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
+ };
+ };
+ };
+ };
+
mdma1: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi
index 92794b942ab2..17d52d93695e 100644
--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
@@ -30,6 +30,74 @@ timer {
};
};
+&cs_funnel {
+ in-ports {
+ port@2 {
+ reg = <2>;
+ funnel_in_port2: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+};
+
+&dbg_bus {
+ cs_cti_cpu1: cti@500d9000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d9000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu1>;
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm1>;
+ };
+ };
+
+ cs_etm1: etm@500dd000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dd000 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_in_port2>;
+ };
+ };
+ };
+ };
+};
+
&etzpc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 08/12] arm: dts: stm32: enable the debug bus on stm32mp1x boards
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (6 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 07/12] arm: dts: stm32: introduce the debug bus for stm32mp1x platforms Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 09/12] arm: dts: stm32: enable CoreSight on stm32mp15xx-dkx boards Gatien Chevallier
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
On stm32mp1x boards, enable the debug bus so we always try to probe
the debug peripherals, if their status and the debug configuration
allow it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 4 ++++
arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 4 ++++
arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 4 ++++
3 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index f894ee35b3db..ebc719797271 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -174,6 +174,10 @@ &cryp {
status = "okay";
};
+&dbg_bus {
+ status = "okay";
+};
+
&dcmipp {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmipp_pins_a>;
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
index 8f99c30f1af1..e69c8e282c8b 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
@@ -81,6 +81,10 @@ &cec {
status = "okay";
};
+&dbg_bus {
+ status = "okay";
+};
+
&dcmi {
status = "okay";
pinctrl-names = "default", "sleep";
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
index 8cea6facd27b..fe2ab07ea4a8 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
@@ -140,6 +140,10 @@ &crc1 {
status = "okay";
};
+&dbg_bus {
+ status = "okay";
+};
+
&dts {
status = "okay";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 09/12] arm: dts: stm32: enable CoreSight on stm32mp15xx-dkx boards
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (7 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 08/12] arm: dts: stm32: enable the debug bus on stm32mp1x boards Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 10/12] arm: dts: stm32: enable CoreSight on the stm32mp157c-ev1 board Gatien Chevallier
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Enable CoreSight peripherals on the stm32mp15xx-dkx boards. All boards
including this file are embedding a dual core SoC so this change is
applicable.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
index fe2ab07ea4a8..c91204476161 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
@@ -140,6 +140,42 @@ &crc1 {
status = "okay";
};
+&cs_cti_trace {
+ status = "okay";
+};
+
+&cs_cti_cpu0 {
+ status = "okay";
+};
+
+&cs_cti_cpu1 {
+ status = "okay";
+};
+
+&cs_etf {
+ status = "okay";
+};
+
+&cs_etm0 {
+ status = "okay";
+};
+
+&cs_etm1 {
+ status = "okay";
+};
+
+&cs_funnel {
+ status = "okay";
+};
+
+&cs_stm {
+ status = "okay";
+};
+
+&cs_tpiu {
+ status = "okay";
+};
+
&dbg_bus {
status = "okay";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 10/12] arm: dts: stm32: enable CoreSight on the stm32mp157c-ev1 board
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (8 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 09/12] arm: dts: stm32: enable CoreSight on stm32mp15xx-dkx boards Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 11/12] arm: dts: stm32: enable CoreSight on the stm32mp135f-dk board Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 12/12] pinctrl: stm32: add firewall checks before probing the HDP driver Gatien Chevallier
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Enable CoreSight peripherals on the stm32mp157c-ev1 board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
index e69c8e282c8b..913c20e31196 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
@@ -81,6 +81,42 @@ &cec {
status = "okay";
};
+&cs_cti_trace {
+ status = "okay";
+};
+
+&cs_cti_cpu0 {
+ status = "okay";
+};
+
+&cs_cti_cpu1 {
+ status = "okay";
+};
+
+&cs_etf {
+ status = "okay";
+};
+
+&cs_etm0 {
+ status = "okay";
+};
+
+&cs_etm1 {
+ status = "okay";
+};
+
+&cs_funnel {
+ status = "okay";
+};
+
+&cs_stm {
+ status = "okay";
+};
+
+&cs_tpiu {
+ status = "okay";
+};
+
&dbg_bus {
status = "okay";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 11/12] arm: dts: stm32: enable CoreSight on the stm32mp135f-dk board
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (9 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 10/12] arm: dts: stm32: enable CoreSight on the stm32mp157c-ev1 board Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 12/12] pinctrl: stm32: add firewall checks before probing the HDP driver Gatien Chevallier
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Enable CoreSight peripherals on the stm32mp135f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index ebc719797271..2ce38e46c6d0 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -174,6 +174,26 @@ &cryp {
status = "okay";
};
+&cs_cti_trace {
+ status = "okay";
+};
+
+&cs_cti_cpu0 {
+ status = "okay";
+};
+
+&cs_etf {
+ status = "okay";
+};
+
+&cs_etm0 {
+ status = "okay";
+};
+
+&cs_tpiu {
+ status = "okay";
+};
+
&dbg_bus {
status = "okay";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 12/12] pinctrl: stm32: add firewall checks before probing the HDP driver
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
` (10 preceding siblings ...)
2026-01-21 12:34 ` [PATCH v3 11/12] arm: dts: stm32: enable CoreSight on the stm32mp135f-dk board Gatien Chevallier
@ 2026-01-21 12:34 ` Gatien Chevallier
11 siblings, 0 replies; 16+ messages in thread
From: Gatien Chevallier @ 2026-01-21 12:34 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Leo Yan,
Clément Le Goffic, Linus Walleij, Maxime Coquelin,
Alexandre Torgue, jens.wiklander
Cc: coresight, linux-arm-kernel, devicetree, linux-kernel, linux-gpio,
linux-stm32, Gatien Chevallier
Because the HDP peripheral both depends on debug and firewall
configuration, when CONFIG_STM32_FIREWALL is present, use the
stm32 firewall framework to be able to check these configuration against
the relevant controllers.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c b/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
index 0b1dff01e04c..cce477e86ef9 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
@@ -4,6 +4,7 @@
* Author: Clément Le Goffic <clement.legoffic@foss.st.com> for STMicroelectronics.
*/
#include <linux/bits.h>
+#include <linux/bus/stm32_firewall_device.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/generic.h>
@@ -46,9 +47,11 @@ struct stm32_hdp {
void __iomem *base;
struct clk *clk;
struct pinctrl_dev *pctl_dev;
+ struct stm32_firewall *firewall;
struct gpio_generic_chip gpio_chip;
u32 mux_conf;
u32 gposet_conf;
+ int nb_firewall_entries;
const char * const *func_name;
};
@@ -615,6 +618,13 @@ static int stm32_hdp_probe(struct platform_device *pdev)
return -ENOMEM;
hdp->dev = dev;
+ if (IS_ENABLED(CONFIG_STM32_FIREWALL)) {
+ err = stm32_firewall_get_grant_all_access(dev, &hdp->firewall,
+ &hdp->nb_firewall_entries);
+ if (err)
+ return err;
+ }
+
platform_set_drvdata(pdev, hdp);
hdp->base = devm_platform_ioremap_resource(pdev, 0);
@@ -670,8 +680,12 @@ static int stm32_hdp_probe(struct platform_device *pdev)
static void stm32_hdp_remove(struct platform_device *pdev)
{
struct stm32_hdp *hdp = platform_get_drvdata(pdev);
+ int i;
writel_relaxed(HDP_CTRL_DISABLE, hdp->base + HDP_CTRL);
+
+ for (i = 0; i < hdp->nb_firewall_entries; i++)
+ stm32_firewall_release_access(&hdp->firewall[i]);
}
static int stm32_hdp_suspend(struct device *dev)
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread