[PATCH 00/10] pci-imx6: Add support for parsing the reset property in new Root Port binding

[PATCH 00/10] pci-imx6: Add support for parsing the reset property in new Root Port binding

[Sherry Sun]

This patch set adds support for parsing the reset property in new Root Port
binding in pci-imx6 driver, similar to the implementation in the qcom pcie
driver[1].

The plan is to add the wake-gpio property to the root port in subsequent
patches. Also, the vpcie-supply property will be moved to the root port
node later based on the refactoring patch set for the PCI pwrctrl
framework[2]. 

[1] https://lore.kernel.org/linux-pci/20250702-perst-v5-0-920b3d1f6ee1@qti.qualcomm.com/
[2] https://lore.kernel.org/linux-pci/20260115-pci-pwrctrl-rework-v5-0-9d26da3ce903@oss.qualcomm.com/

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
Sherry Sun (10):
  dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
  PCI: imx6: Add support for parsing the reset property in new Root Port
    binding
  arm: dts: imx6qdl: Add Root Port node and move PERST property to Root
    Port node
  arm: dts: imx6sx: Add Root Port node and move PERST property to Root
    Port node
  arm: dts: imx7d: Add Root Port node and move PERST property to Root
    Port node
  arm64: dts: imx8mm: Add Root Port node and move PERST property to Root
    Port node
  arm64: dts: imx8mp: Add Root Port node and move PERST property to Root
    Port node
  arm64: dts: imx8mq: Add Root Port nodes and move PERST property to
    Root Port node
  arm64: dts: imx8dxl/qm/qxp: Add Root Port nodes and move PERST
    property to Root Port node
  arm64: dts: imx95: Add Root Port nodes and move PERST property to Root
    Port node

 .../bindings/pci/fsl,imx6q-pcie.yaml          |  29 ++++
 .../arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |   5 +-
 arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi        |  11 ++
 .../arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |   5 +-
 arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi     |   5 +-
 arch/arm/boot/dts/nxp/imx/imx6sx.dtsi         |  11 ++
 arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts       |   5 +-
 arch/arm/boot/dts/nxp/imx/imx7d.dtsi          |  11 ++
 .../boot/dts/freescale/imx8-ss-hsio.dtsi      |  11 ++
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts |   5 +-
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |   5 +-
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  11 ++
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts  |   5 +-
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     |  11 ++
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts  |  10 +-
 arch/arm64/boot/dts/freescale/imx8mq.dtsi     |  22 +++
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts  |  10 +-
 .../boot/dts/freescale/imx8qm-ss-hsio.dtsi    |  22 +++
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts |   5 +-
 .../boot/dts/freescale/imx95-15x15-evk.dts    |   5 +-
 .../boot/dts/freescale/imx95-19x19-evk.dts    |  10 +-
 arch/arm64/boot/dts/freescale/imx95.dtsi      |  22 +++
 drivers/pci/controller/dwc/pci-imx6.c         | 128 ++++++++++++++++--
 23 files changed, 335 insertions(+), 29 deletions(-)

-- 
2.37.1

[PATCH 01/10] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node

[Sherry Sun]

Update the fsl,imx6q-pcie.yaml to include the reset-gpios property in
the Root Port node.

There is already 'reset-gpios' property defined for PERST# in
pci-bus-common.yaml, so use that property instead of 'reset-gpio' in
this file, for backward compatibility, do not remove the existing
property in the bridge node, but mark them as 'deprecated' instead.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 12a01f7a5744..74156b42e7a2 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -59,9 +59,12 @@ properties:
       - const: dma
 
   reset-gpio:
+    deprecated: true
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
       sequence (L=reset state, H=operation state) (optional required).
+      This property is deprecated, instead of referencing this property from the
+      host bridge node, use the reset-gpios property from the root port node.
 
   reset-gpio-active-high:
     description: If present then the reset sequence using the GPIO
@@ -69,6 +72,18 @@ properties:
       L=operation state) (optional required).
     type: boolean
 
+  pcie@0:
+    description:
+      Describe the i.MX6 PCIe Root Port.
+    type: object
+    $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+    properties:
+      reg:
+        maxItems: 1
+
+    unevaluatedProperties: false
+
 required:
   - compatible
   - reg
@@ -229,6 +244,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/imx6qdl-clock.h>
+    #include <dt-bindings/gpio/gpio.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     pcie: pcie@1ffc000 {
@@ -255,5 +271,18 @@ examples:
                 <&clks IMX6QDL_CLK_LVDS1_GATE>,
                 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
         clock-names = "pcie", "pcie_bus", "pcie_phy";
+
+        pcie_port0: pcie@0 {
+            compatible = "pciclass,0604";
+            device_type = "pci";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            bus-range = <0x01 0xff>;
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+        };
     };
 ...
-- 
2.37.1

Re: [PATCH 01/10] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node

[Frank Li]

On Mon, Jan 19, 2026 at 06:02:26PM +0800, Sherry Sun wrote:
> Update the fsl,imx6q-pcie.yaml to include the reset-gpios property in
> the Root Port node.
>
> There is already 'reset-gpios' property defined for PERST# in
> pci-bus-common.yaml, so use that property instead of 'reset-gpio' in
> this file, for backward compatibility, do not remove the existing
> property in the bridge node, but mark them as 'deprecated' instead.


Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property
for the Root Port node.

The reset-gpios property is already defined in pci-bus-common.yaml for
PERST#, so use it instead of the local reset-gpio property. Keep the
existing reset-gpio property in the bridge node for backward
compatibility, but mark it as deprecated.


Frank
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>  .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 12a01f7a5744..74156b42e7a2 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -59,9 +59,12 @@ properties:
>        - const: dma
>
>    reset-gpio:
> +    deprecated: true
>      description: Should specify the GPIO for controlling the PCI bus device
>        reset signal. It's not polarity aware and defaults to active-low reset
>        sequence (L=reset state, H=operation state) (optional required).
> +      This property is deprecated, instead of referencing this property from the
> +      host bridge node, use the reset-gpios property from the root port node.
>
>    reset-gpio-active-high:
>      description: If present then the reset sequence using the GPIO
> @@ -69,6 +72,18 @@ properties:
>        L=operation state) (optional required).
>      type: boolean
>
> +  pcie@0:
> +    description:
> +      Describe the i.MX6 PCIe Root Port.
> +    type: object
> +    $ref: /schemas/pci/pci-pci-bridge.yaml#
> +
> +    properties:
> +      reg:
> +        maxItems: 1
> +
> +    unevaluatedProperties: false
> +
>  required:
>    - compatible
>    - reg
> @@ -229,6 +244,7 @@ unevaluatedProperties: false
>  examples:
>    - |
>      #include <dt-bindings/clock/imx6qdl-clock.h>
> +    #include <dt-bindings/gpio/gpio.h>
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>
>      pcie: pcie@1ffc000 {
> @@ -255,5 +271,18 @@ examples:
>                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
>                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
>          clock-names = "pcie", "pcie_bus", "pcie_phy";
> +
> +        pcie_port0: pcie@0 {
> +            compatible = "pciclass,0604";
> +            device_type = "pci";
> +            reg = <0x0 0x0 0x0 0x0 0x0>;
> +            bus-range = <0x01 0xff>;
> +
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +            ranges;
> +
> +            reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
> +        };
>      };
>  ...
> --
> 2.37.1
>

RE: [PATCH 01/10] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node

[Sherry Sun]

> On Mon, Jan 19, 2026 at 06:02:26PM +0800, Sherry Sun wrote:
> > Update the fsl,imx6q-pcie.yaml to include the reset-gpios property in
> > the Root Port node.
> >
> > There is already 'reset-gpios' property defined for PERST# in
> > pci-bus-common.yaml, so use that property instead of 'reset-gpio' in
> > this file, for backward compatibility, do not remove the existing
> > property in the bridge node, but mark them as 'deprecated' instead.
> 
> 
> Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property for
> the Root Port node.
> 
> The reset-gpios property is already defined in pci-bus-common.yaml for
> PERST#, so use it instead of the local reset-gpio property. Keep the existing
> reset-gpio property in the bridge node for backward compatibility, but mark it
> as deprecated.
> 

Hi Frank, ok, will improve the commit message in V2, thanks!

Best Regards
Sherry

> 
> Frank
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 12a01f7a5744..74156b42e7a2 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -59,9 +59,12 @@ properties:
> >        - const: dma
> >
> >    reset-gpio:
> > +    deprecated: true
> >      description: Should specify the GPIO for controlling the PCI bus device
> >        reset signal. It's not polarity aware and defaults to active-low reset
> >        sequence (L=reset state, H=operation state) (optional required).
> > +      This property is deprecated, instead of referencing this property from
> the
> > +      host bridge node, use the reset-gpios property from the root port
> node.
> >
> >    reset-gpio-active-high:
> >      description: If present then the reset sequence using the GPIO @@
> > -69,6 +72,18 @@ properties:
> >        L=operation state) (optional required).
> >      type: boolean
> >
> > +  pcie@0:
> > +    description:
> > +      Describe the i.MX6 PCIe Root Port.
> > +    type: object
> > +    $ref: /schemas/pci/pci-pci-bridge.yaml#
> > +
> > +    properties:
> > +      reg:
> > +        maxItems: 1
> > +
> > +    unevaluatedProperties: false
> > +
> >  required:
> >    - compatible
> >    - reg
> > @@ -229,6 +244,7 @@ unevaluatedProperties: false
> >  examples:
> >    - |
> >      #include <dt-bindings/clock/imx6qdl-clock.h>
> > +    #include <dt-bindings/gpio/gpio.h>
> >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> >
> >      pcie: pcie@1ffc000 {
> > @@ -255,5 +271,18 @@ examples:
> >                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
> >                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> >          clock-names = "pcie", "pcie_bus", "pcie_phy";
> > +
> > +        pcie_port0: pcie@0 {
> > +            compatible = "pciclass,0604";
> > +            device_type = "pci";
> > +            reg = <0x0 0x0 0x0 0x0 0x0>;
> > +            bus-range = <0x01 0xff>;
> > +
> > +            #address-cells = <3>;
> > +            #size-cells = <2>;
> > +            ranges;
> > +
> > +            reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
> > +        };
> >      };
> >  ...
> > --
> > 2.37.1
> >

Re: [PATCH 01/10] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node

[Rob Herring]

On Mon, Jan 19, 2026 at 06:02:26PM +0800, Sherry Sun wrote:
> Update the fsl,imx6q-pcie.yaml to include the reset-gpios property in
> the Root Port node.
> 
> There is already 'reset-gpios' property defined for PERST# in
> pci-bus-common.yaml, so use that property instead of 'reset-gpio' in
> this file, for backward compatibility, do not remove the existing
> property in the bridge node, but mark them as 'deprecated' instead.
> 
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>  .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 12a01f7a5744..74156b42e7a2 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -59,9 +59,12 @@ properties:
>        - const: dma
>  
>    reset-gpio:
> +    deprecated: true
>      description: Should specify the GPIO for controlling the PCI bus device
>        reset signal. It's not polarity aware and defaults to active-low reset
>        sequence (L=reset state, H=operation state) (optional required).
> +      This property is deprecated, instead of referencing this property from the
> +      host bridge node, use the reset-gpios property from the root port node.
>  
>    reset-gpio-active-high:

Probably this needs to be deprecated too?

>      description: If present then the reset sequence using the GPIO

RE: [PATCH 01/10] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node

[Sherry Sun]

> On Mon, Jan 19, 2026 at 06:02:26PM +0800, Sherry Sun wrote:
> > Update the fsl,imx6q-pcie.yaml to include the reset-gpios property in
> > the Root Port node.
> >
> > There is already 'reset-gpios' property defined for PERST# in
> > pci-bus-common.yaml, so use that property instead of 'reset-gpio' in
> > this file, for backward compatibility, do not remove the existing
> > property in the bridge node, but mark them as 'deprecated' instead.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 12a01f7a5744..74156b42e7a2 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -59,9 +59,12 @@ properties:
> >        - const: dma
> >
> >    reset-gpio:
> > +    deprecated: true
> >      description: Should specify the GPIO for controlling the PCI bus device
> >        reset signal. It's not polarity aware and defaults to active-low reset
> >        sequence (L=reset state, H=operation state) (optional required).
> > +      This property is deprecated, instead of referencing this property from
> the
> > +      host bridge node, use the reset-gpios property from the root port
> node.
> >
> >    reset-gpio-active-high:
> 
> Probably this needs to be deprecated too?

Hi Rob,
Yes, I will also mark this property as deprecated in V2, thanks!

Best Regards
Sherry

> 
> >      description: If present then the reset sequence using the GPIO

[PATCH 02/10] PCI: imx6: Add support for parsing the reset property in new Root Port binding

[Sherry Sun]

DT binding allows specifying 'reset' property in both host bridge and
Root Port nodes, but specifying in the host bridge node is marked as
deprecated. So add support for parsing the new binding that uses
'reset-gpios' property for PERST#.

To maintain DT backwards compatibility, fallback to the legacy method of
parsing the host bridge node if the reset property is not present in the
Root Port node.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 128 +++++++++++++++++++++++---
 1 file changed, 114 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 1d8677d7de04..0592b24071bc 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -147,10 +147,15 @@ struct imx_lut_data {
 	u32 data2;
 };
 
+struct imx_pcie_port {
+	struct list_head	list;
+	struct gpio_desc	*reset;
+};
+
 struct imx_pcie {
 	struct dw_pcie		*pci;
-	struct gpio_desc	*reset_gpiod;
 	struct clk_bulk_data	*clks;
+	struct list_head	ports;
 	int			num_clks;
 	bool			supports_clkreq;
 	bool			enable_ext_refclk;
@@ -896,29 +901,35 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 
 static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
 {
+	struct imx_pcie_port *port;
+
 	reset_control_assert(imx_pcie->pciephy_reset);
 
 	if (imx_pcie->drvdata->core_reset)
 		imx_pcie->drvdata->core_reset(imx_pcie, true);
 
 	/* Some boards don't have PCIe reset GPIO. */
-	gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
+	list_for_each_entry(port, &imx_pcie->ports, list)
+		gpiod_set_value_cansleep(port->reset, 1);
 }
 
 static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
 {
+	struct imx_pcie_port *port;
+
 	reset_control_deassert(imx_pcie->pciephy_reset);
 
 	if (imx_pcie->drvdata->core_reset)
 		imx_pcie->drvdata->core_reset(imx_pcie, false);
 
 	/* Some boards don't have PCIe reset GPIO. */
-	if (imx_pcie->reset_gpiod) {
-		msleep(100);
-		gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
-		/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
-		msleep(100);
-	}
+	list_for_each_entry(port, &imx_pcie->ports, list)
+		if (port->reset) {
+			msleep(100);
+			gpiod_set_value_cansleep(port->reset, 0);
+			/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
+			msleep(100);
+		}
 
 	return 0;
 }
@@ -1638,6 +1649,81 @@ static const struct dev_pm_ops imx_pcie_pm_ops = {
 				  imx_pcie_resume_noirq)
 };
 
+static int imx_pcie_parse_port(struct imx_pcie *pcie, struct device_node *node)
+{
+	struct device *dev = pcie->pci->dev;
+	struct imx_pcie_port *port;
+	struct gpio_desc *reset;
+
+	reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
+				      "reset", GPIOD_OUT_HIGH, "PCIe reset");
+	if (IS_ERR(reset))
+		return PTR_ERR(reset);
+
+	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	port->reset = reset;
+	INIT_LIST_HEAD(&port->list);
+	list_add_tail(&port->list, &pcie->ports);
+
+	return 0;
+}
+
+static int imx_pcie_parse_ports(struct imx_pcie *pcie)
+{
+	struct device *dev = pcie->pci->dev;
+	struct imx_pcie_port *port, *tmp;
+	int ret = -ENOENT;
+
+	for_each_available_child_of_node_scoped(dev->of_node, of_port) {
+		if (!of_node_is_type(of_port, "pci"))
+			continue;
+		ret = imx_pcie_parse_port(pcie, of_port);
+		if (ret)
+			goto err_port_del;
+	}
+
+	return ret;
+
+err_port_del:
+	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
+		list_del(&port->list);
+
+	return ret;
+}
+
+static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)
+{
+	struct device *dev = pcie->pci->dev;
+	struct imx_pcie_port *port;
+	struct gpio_desc *reset;
+
+	reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(reset))
+		return PTR_ERR(reset);
+
+	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	port->reset = reset;
+	INIT_LIST_HEAD(&port->list);
+	list_add_tail(&port->list, &pcie->ports);
+
+	return 0;
+}
+
+static void imx_pcie_delete_ports(void *data)
+{
+	struct imx_pcie *pcie = data;
+	struct imx_pcie_port *port, *tmp;
+
+	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
+		list_del(&port->list);
+}
+
 static int imx_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1656,6 +1742,8 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	if (!pci)
 		return -ENOMEM;
 
+	INIT_LIST_HEAD(&imx_pcie->ports);
+
 	pci->dev = dev;
 	pci->ops = &dw_pcie_ops;
 
@@ -1684,12 +1772,24 @@ static int imx_pcie_probe(struct platform_device *pdev)
 			return PTR_ERR(imx_pcie->phy_base);
 	}
 
-	/* Fetch GPIOs */
-	imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
-	if (IS_ERR(imx_pcie->reset_gpiod))
-		return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
-				     "unable to get reset gpio\n");
-	gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
+	ret = imx_pcie_parse_ports(imx_pcie);
+	if (ret) {
+		if (ret != -ENOENT)
+			return dev_err_probe(dev, ret, "Failed to parse Root Port: %d\n", ret);
+
+		/*
+		 * In the case of properties not populated in Root Port node,
+		 * fallback to the legacy method of parsing the Host Bridge
+		 * node. This is to maintain DT backwards compatibility.
+		 */
+		ret = imx_pcie_parse_legacy_binding(imx_pcie);
+		if (ret)
+			return dev_err_probe(dev, ret, "Unable to get reset gpio: %d\n", ret);
+	}
+
+	ret = devm_add_action_or_reset(dev, imx_pcie_delete_ports, imx_pcie);
+	if (ret)
+		return ret;
 
 	/* Fetch clocks */
 	imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
-- 
2.37.1

Re: [PATCH 02/10] PCI: imx6: Add support for parsing the reset property in new Root Port binding

[Frank Li]

On Mon, Jan 19, 2026 at 06:02:27PM +0800, Sherry Sun wrote:
> DT binding allows specifying 'reset' property in both host bridge and
> Root Port nodes, but specifying in the host bridge node is marked as
> deprecated. So add support for parsing the new binding that uses
> 'reset-gpios' property for PERST#.
>
> To maintain DT backwards compatibility, fallback to the legacy method of
> parsing the host bridge node if the reset property is not present in the
> Root Port node.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 128 +++++++++++++++++++++++---
>  1 file changed, 114 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 1d8677d7de04..0592b24071bc 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -147,10 +147,15 @@ struct imx_lut_data {
>  	u32 data2;
>  };
>
> +
> +static int imx_pcie_parse_ports(struct imx_pcie *pcie)
> +{
> +	struct device *dev = pcie->pci->dev;
> +	struct imx_pcie_port *port, *tmp;
> +	int ret = -ENOENT;
> +
> +	for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> +		if (!of_node_is_type(of_port, "pci"))
> +			continue;
> +		ret = imx_pcie_parse_port(pcie, of_port);
> +		if (ret)
> +			goto err_port_del;
> +	}
> +
> +	return ret;
> +
> +err_port_del:
> +	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
> +		list_del(&port->list);

you can call helper imx_pcie_delete_ports()

Frank
> +
> +	return ret;
> +}
> +
> +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)
> +{
> +	struct device *dev = pcie->pci->dev;
> +	struct imx_pcie_port *port;
> +	struct gpio_desc *reset;
> +
> +	reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> +	if (IS_ERR(reset))
> +		return PTR_ERR(reset);
> +
> +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> +	if (!port)
> +		return -ENOMEM;
> +
> +	port->reset = reset;
> +	INIT_LIST_HEAD(&port->list);
> +	list_add_tail(&port->list, &pcie->ports);
> +
> +	return 0;
> +}
> +
> +static void imx_pcie_delete_ports(void *data)
> +{
> +	struct imx_pcie *pcie = data;
> +	struct imx_pcie_port *port, *tmp;
> +
> +	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
> +		list_del(&port->list);
> +}
> +
>  static int imx_pcie_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -1656,6 +1742,8 @@ static int imx_pcie_probe(struct platform_device *pdev)
>  	if (!pci)
>  		return -ENOMEM;
>
> +	INIT_LIST_HEAD(&imx_pcie->ports);
> +
>  	pci->dev = dev;
>  	pci->ops = &dw_pcie_ops;
>
> @@ -1684,12 +1772,24 @@ static int imx_pcie_probe(struct platform_device *pdev)
>  			return PTR_ERR(imx_pcie->phy_base);
>  	}
>
> -	/* Fetch GPIOs */
> -	imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> -	if (IS_ERR(imx_pcie->reset_gpiod))
> -		return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
> -				     "unable to get reset gpio\n");
> -	gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
> +	ret = imx_pcie_parse_ports(imx_pcie);
> +	if (ret) {
> +		if (ret != -ENOENT)
> +			return dev_err_probe(dev, ret, "Failed to parse Root Port: %d\n", ret);
> +
> +		/*
> +		 * In the case of properties not populated in Root Port node,
> +		 * fallback to the legacy method of parsing the Host Bridge
> +		 * node. This is to maintain DT backwards compatibility.
> +		 */
> +		ret = imx_pcie_parse_legacy_binding(imx_pcie);
> +		if (ret)
> +			return dev_err_probe(dev, ret, "Unable to get reset gpio: %d\n", ret);
> +	}
> +
> +	ret = devm_add_action_or_reset(dev, imx_pcie_delete_ports, imx_pcie);
> +	if (ret)
> +		return ret;
>
>  	/* Fetch clocks */
>  	imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
> --
> 2.37.1
>

RE: [PATCH 02/10] PCI: imx6: Add support for parsing the reset property in new Root Port binding

[Sherry Sun]

> Subject: Re: [PATCH 02/10] PCI: imx6: Add support for parsing the reset
> property in new Root Port binding
> 
> On Mon, Jan 19, 2026 at 06:02:27PM +0800, Sherry Sun wrote:
> > DT binding allows specifying 'reset' property in both host bridge and
> > Root Port nodes, but specifying in the host bridge node is marked as
> > deprecated. So add support for parsing the new binding that uses
> > 'reset-gpios' property for PERST#.
> >
> > To maintain DT backwards compatibility, fallback to the legacy method
> > of parsing the host bridge node if the reset property is not present
> > in the Root Port node.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 128
> > +++++++++++++++++++++++---
> >  1 file changed, 114 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 1d8677d7de04..0592b24071bc 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -147,10 +147,15 @@ struct imx_lut_data {
> >  	u32 data2;
> >  };
> >
> > +
> > +static int imx_pcie_parse_ports(struct imx_pcie *pcie) {
> > +	struct device *dev = pcie->pci->dev;
> > +	struct imx_pcie_port *port, *tmp;
> > +	int ret = -ENOENT;
> > +
> > +	for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > +		if (!of_node_is_type(of_port, "pci"))
> > +			continue;
> > +		ret = imx_pcie_parse_port(pcie, of_port);
> > +		if (ret)
> > +			goto err_port_del;
> > +	}
> > +
> > +	return ret;
> > +
> > +err_port_del:
> > +	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
> > +		list_del(&port->list);
> 
> you can call helper imx_pcie_delete_ports()

Sure, will fix in V2, thanks!

Best Regards
Sherry

> 
> Frank
> > +
> > +	return ret;
> > +}
> > +
> > +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) {
> > +	struct device *dev = pcie->pci->dev;
> > +	struct imx_pcie_port *port;
> > +	struct gpio_desc *reset;
> > +
> > +	reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> > +	if (IS_ERR(reset))
> > +		return PTR_ERR(reset);
> > +
> > +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > +	if (!port)
> > +		return -ENOMEM;
> > +
> > +	port->reset = reset;
> > +	INIT_LIST_HEAD(&port->list);
> > +	list_add_tail(&port->list, &pcie->ports);
> > +
> > +	return 0;
> > +}
> > +
> > +static void imx_pcie_delete_ports(void *data) {
> > +	struct imx_pcie *pcie = data;
> > +	struct imx_pcie_port *port, *tmp;
> > +
> > +	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
> > +		list_del(&port->list);
> > +}
> > +
> >  static int imx_pcie_probe(struct platform_device *pdev)  {
> >  	struct device *dev = &pdev->dev;
> > @@ -1656,6 +1742,8 @@ static int imx_pcie_probe(struct platform_device
> *pdev)
> >  	if (!pci)
> >  		return -ENOMEM;
> >
> > +	INIT_LIST_HEAD(&imx_pcie->ports);
> > +
> >  	pci->dev = dev;
> >  	pci->ops = &dw_pcie_ops;
> >
> > @@ -1684,12 +1772,24 @@ static int imx_pcie_probe(struct
> platform_device *pdev)
> >  			return PTR_ERR(imx_pcie->phy_base);
> >  	}
> >
> > -	/* Fetch GPIOs */
> > -	imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset",
> GPIOD_OUT_HIGH);
> > -	if (IS_ERR(imx_pcie->reset_gpiod))
> > -		return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
> > -				     "unable to get reset gpio\n");
> > -	gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
> > +	ret = imx_pcie_parse_ports(imx_pcie);
> > +	if (ret) {
> > +		if (ret != -ENOENT)
> > +			return dev_err_probe(dev, ret, "Failed to parse Root
> Port: %d\n",
> > +ret);
> > +
> > +		/*
> > +		 * In the case of properties not populated in Root Port node,
> > +		 * fallback to the legacy method of parsing the Host Bridge
> > +		 * node. This is to maintain DT backwards compatibility.
> > +		 */
> > +		ret = imx_pcie_parse_legacy_binding(imx_pcie);
> > +		if (ret)
> > +			return dev_err_probe(dev, ret, "Unable to get reset
> gpio: %d\n", ret);
> > +	}
> > +
> > +	ret = devm_add_action_or_reset(dev, imx_pcie_delete_ports,
> imx_pcie);
> > +	if (ret)
> > +		return ret;
> >
> >  	/* Fetch clocks */
> >  	imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
> > --
> > 2.37.1
> >

[PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |  5 ++++-
 arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi         | 11 +++++++++++
 arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |  5 ++++-
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
index ba29720e3f72..c64c8cbd0038 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
@@ -754,11 +754,14 @@ lvds0_out: endpoint {
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
-	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie>;
 	status = "okay";
 };
 
+&pcie_port0 {
+	reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+};
+
 &pwm1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index 9793feee6394..c03deb2cdfab 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -287,6 +287,17 @@ pcie: pcie@1ffc000 {
 				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 			clock-names = "pcie", "pcie_bus", "pcie_phy";
 			status = "disabled";
+
+			pcie_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		aips1: bus@2000000 { /* AIPS1 */
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
index c5b220aeaefd..c35c24623d36 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
@@ -45,10 +45,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 };
 
 &pcie {
-	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
+&pcie_port0 {
+	reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+};
+
 &sata {
 	status = "okay";
 };
-- 
2.37.1

Re: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move PERST property to Root Port node

[Frank Li]

On Mon, Jan 19, 2026 at 06:02:28PM +0800, Sherry Sun wrote:
> Since describing the PCIe PERST# property under Host Bridge node is now
> deprecated, it is recommended to add it to the Root Port node, so
> creating the Root Port node and move the reset-gpios property.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>  arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |  5 ++++-
>  arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi         | 11 +++++++++++
>  arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |  5 ++++-
>  3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> index ba29720e3f72..c64c8cbd0038 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> @@ -754,11 +754,14 @@ lvds0_out: endpoint {
>  &pcie {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie>;
> -	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;

Generally, don't remove old property to keep back comaptiblity. You can
add comments here if you want.

Frank

>  	vpcie-supply = <&reg_pcie>;
>  	status = "okay";
>  };
>
> +&pcie_port0 {
> +	reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
> +};
> +
>  &pwm1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pwm1>;
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> index 9793feee6394..c03deb2cdfab 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> @@ -287,6 +287,17 @@ pcie: pcie@1ffc000 {
>  				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
>  			clock-names = "pcie", "pcie_bus", "pcie_phy";
>  			status = "disabled";
> +
> +			pcie_port0: pcie@0 {
> +				compatible = "pciclass,0604";
> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +			};
>  		};
>
>  		aips1: bus@2000000 { /* AIPS1 */
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> index c5b220aeaefd..c35c24623d36 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> @@ -45,10 +45,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
>  };
>
>  &pcie {
> -	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  };
>
> +&pcie_port0 {
> +	reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> +};
> +
>  &sata {
>  	status = "okay";
>  };
> --
> 2.37.1
>

RE: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

> Subject: Re: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move
> PERST property to Root Port node
> 
> On Mon, Jan 19, 2026 at 06:02:28PM +0800, Sherry Sun wrote:
> > Since describing the PCIe PERST# property under Host Bridge node is
> > now deprecated, it is recommended to add it to the Root Port node, so
> > creating the Root Port node and move the reset-gpios property.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> >  arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |  5 ++++-
> >  arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi         | 11 +++++++++++
> >  arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |  5 ++++-
> >  3 files changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > index ba29720e3f72..c64c8cbd0038 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > @@ -754,11 +754,14 @@ lvds0_out: endpoint {  &pcie {
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <&pinctrl_pcie>;
> > -	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> 
> Generally, don't remove old property to keep back comaptiblity. You can add
> comments here if you want.

Hi Frank,
Actually not remove, just move the property from host bridge node to
the Root Port node, if keep both reset-gpios property in dts, not sure if it may
confuse users because it's unclear which one is the valid configuration.

Best Regards
Sherry
> 
> Frank
> 
> >  	vpcie-supply = <&reg_pcie>;
> >  	status = "okay";
> >  };
> >
> > +&pcie_port0 {
> > +	reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; };
> > +
> >  &pwm1 {
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <&pinctrl_pwm1>;
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > index 9793feee6394..c03deb2cdfab 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > @@ -287,6 +287,17 @@ pcie: pcie@1ffc000 {
> >  				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> >  			clock-names = "pcie", "pcie_bus", "pcie_phy";
> >  			status = "disabled";
> > +
> > +			pcie_port0: pcie@0 {
> > +				compatible = "pciclass,0604";
> > +				device_type = "pci";
> > +				reg = <0x0 0x0 0x0 0x0 0x0>;
> > +				bus-range = <0x01 0xff>;
> > +
> > +				#address-cells = <3>;
> > +				#size-cells = <2>;
> > +				ranges;
> > +			};
> >  		};
> >
> >  		aips1: bus@2000000 { /* AIPS1 */
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > index c5b220aeaefd..c35c24623d36 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > @@ -45,10 +45,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ
> 	0x000b1
> >  };
> >
> >  &pcie {
> > -	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> >  	status = "okay";
> >  };
> >
> > +&pcie_port0 {
> > +	reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>; };
> > +
> >  &sata {
> >  	status = "okay";
> >  };
> > --
> > 2.37.1
> >

Re: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move PERST property to Root Port node

[Frank Li]

On Tue, Jan 20, 2026 at 02:44:34AM +0000, Sherry Sun wrote:
>
> > Subject: Re: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move
> > PERST property to Root Port node
> >
> > On Mon, Jan 19, 2026 at 06:02:28PM +0800, Sherry Sun wrote:
> > > Since describing the PCIe PERST# property under Host Bridge node is
> > > now deprecated, it is recommended to add it to the Root Port node, so
> > > creating the Root Port node and move the reset-gpios property.
> > >
> > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > ---
> > >  arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |  5 ++++-
> > >  arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi         | 11 +++++++++++
> > >  arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |  5 ++++-
> > >  3 files changed, 19 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > index ba29720e3f72..c64c8cbd0038 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > @@ -754,11 +754,14 @@ lvds0_out: endpoint {  &pcie {
> > >  	pinctrl-names = "default";
> > >  	pinctrl-0 = <&pinctrl_pcie>;
> > > -	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> >
> > Generally, don't remove old property to keep back comaptiblity. You can add
> > comments here if you want.
>
> Hi Frank,
> Actually not remove, just move the property from host bridge node to
> the Root Port node, if keep both reset-gpios property in dts, not sure if it may
> confuse users because it's unclear which one is the valid configuration.

You can add comments here. Just in case this dts use by old kernel. At
least keep some kernel release, then remove it later.

Remove it at least need wait for pci part driver merged.

Frank
>
> Best Regards
> Sherry
> >
> > Frank
> >
> > >  	vpcie-supply = <&reg_pcie>;
> > >  	status = "okay";
> > >  };
> > >
> > > +&pcie_port0 {
> > > +	reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; };
> > > +
> > >  &pwm1 {
> > >  	pinctrl-names = "default";
> > >  	pinctrl-0 = <&pinctrl_pwm1>;
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > index 9793feee6394..c03deb2cdfab 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > @@ -287,6 +287,17 @@ pcie: pcie@1ffc000 {
> > >  				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> > >  			clock-names = "pcie", "pcie_bus", "pcie_phy";
> > >  			status = "disabled";
> > > +
> > > +			pcie_port0: pcie@0 {
> > > +				compatible = "pciclass,0604";
> > > +				device_type = "pci";
> > > +				reg = <0x0 0x0 0x0 0x0 0x0>;
> > > +				bus-range = <0x01 0xff>;
> > > +
> > > +				#address-cells = <3>;
> > > +				#size-cells = <2>;
> > > +				ranges;
> > > +			};
> > >  		};
> > >
> > >  		aips1: bus@2000000 { /* AIPS1 */
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > index c5b220aeaefd..c35c24623d36 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > @@ -45,10 +45,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ
> > 	0x000b1
> > >  };
> > >
> > >  &pcie {
> > > -	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> > >  	status = "okay";
> > >  };
> > >
> > > +&pcie_port0 {
> > > +	reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>; };
> > > +
> > >  &sata {
> > >  	status = "okay";
> > >  };
> > > --
> > > 2.37.1
> > >

RE: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

> Subject: Re: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and move
> PERST property to Root Port node
> 
> On Tue, Jan 20, 2026 at 02:44:34AM +0000, Sherry Sun wrote:
> >
> > > Subject: Re: [PATCH 03/10] arm: dts: imx6qdl: Add Root Port node and
> > > move PERST property to Root Port node
> > >
> > > On Mon, Jan 19, 2026 at 06:02:28PM +0800, Sherry Sun wrote:
> > > > Since describing the PCIe PERST# property under Host Bridge node
> > > > is now deprecated, it is recommended to add it to the Root Port
> > > > node, so creating the Root Port node and move the reset-gpios property.
> > > >
> > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > > ---
> > > >  arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |  5 ++++-
> > > >  arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi         | 11 +++++++++++
> > > >  arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |  5 ++++-
> > > >  3 files changed, 19 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > > b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > > index ba29720e3f72..c64c8cbd0038 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > > @@ -754,11 +754,14 @@ lvds0_out: endpoint {  &pcie {
> > > >  	pinctrl-names = "default";
> > > >  	pinctrl-0 = <&pinctrl_pcie>;
> > > > -	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> > >
> > > Generally, don't remove old property to keep back comaptiblity. You
> > > can add comments here if you want.
> >
> > Hi Frank,
> > Actually not remove, just move the property from host bridge node to
> > the Root Port node, if keep both reset-gpios property in dts, not sure
> > if it may confuse users because it's unclear which one is the valid configuration.
> 
> You can add comments here. Just in case this dts use by old kernel. At least keep
> some kernel release, then remove it later.
> 
> Remove it at least need wait for pci part driver merged.

Hi Frank,
Ok, understand, will keep the old property for these dts files in V2.

Best Regards
Sherry

> 
> Frank
> >
> > Best Regards
> > Sherry
> > >
> > > Frank
> > >
> > > >  	vpcie-supply = <&reg_pcie>;
> > > >  	status = "okay";
> > > >  };
> > > >
> > > > +&pcie_port0 {
> > > > +	reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; };
> > > > +
> > > >  &pwm1 {
> > > >  	pinctrl-names = "default";
> > > >  	pinctrl-0 = <&pinctrl_pwm1>;
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > > b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > > index 9793feee6394..c03deb2cdfab 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > > > @@ -287,6 +287,17 @@ pcie: pcie@1ffc000 {
> > > >  				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> > > >  			clock-names = "pcie", "pcie_bus", "pcie_phy";
> > > >  			status = "disabled";
> > > > +
> > > > +			pcie_port0: pcie@0 {
> > > > +				compatible = "pciclass,0604";
> > > > +				device_type = "pci";
> > > > +				reg = <0x0 0x0 0x0 0x0 0x0>;
> > > > +				bus-range = <0x01 0xff>;
> > > > +
> > > > +				#address-cells = <3>;
> > > > +				#size-cells = <2>;
> > > > +				ranges;
> > > > +			};
> > > >  		};
> > > >
> > > >  		aips1: bus@2000000 { /* AIPS1 */ diff --git
> > > > a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > > b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > > index c5b220aeaefd..c35c24623d36 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > > > @@ -45,10 +45,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ
> > > 	0x000b1
> > > >  };
> > > >
> > > >  &pcie {
> > > > -	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> > > >  	status = "okay";
> > > >  };
> > > >
> > > > +&pcie_port0 {
> > > > +	reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>; };
> > > > +
> > > >  &sata {
> > > >  	status = "okay";
> > > >  };
> > > > --
> > > > 2.37.1
> > > >

[PATCH 04/10] arm: dts: imx6sx: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi |  5 ++++-
 arch/arm/boot/dts/nxp/imx/imx6sx.dtsi     | 11 +++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
index 3e238d8118fa..a4170486529f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
@@ -282,11 +282,14 @@ codec: wm8962@1a {
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
-	reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie_gpio>;
 	status = "okay";
 };
 
+&pcie_port0 {
+	reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+};
+
 &lcdif1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcd>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
index 5132b575b001..c04436f4cf0d 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
@@ -1470,6 +1470,17 @@ pcie: pcie@8ffc000 {
 			power-domains = <&pd_disp>, <&pd_pci>;
 			power-domain-names = "pcie", "pcie_phy";
 			status = "disabled";
+
+			pcie_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 	};
 };
-- 
2.37.1

[PATCH 05/10] arm: dts: imx7d: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts |  5 ++++-
 arch/arm/boot/dts/nxp/imx/imx7d.dtsi    | 11 +++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
index a370e868cafe..e8fe57d6162f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
@@ -456,10 +456,13 @@ display_out: endpoint {
 };
 
 &pcie {
-	reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
+&pcie_port0 {
+	reset-gpios = <&extended_io 1 GPIO_ACTIVE_LOW>;
+};
+
 &reg_1p0d {
 	vin-supply = <&sw2_reg>;
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
index d961c61a93af..3c5c1f2c1460 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
@@ -155,6 +155,17 @@ pcie: pcie@33800000 {
 			reset-names = "pciephy", "apps", "turnoff";
 			fsl,imx7d-pcie-phy = <&pcie_phy>;
 			status = "disabled";
+
+			pcie_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 	};
 };
-- 
2.37.1

[PATCH 06/10] arm64: dts: imx8mm: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |  5 ++++-
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 11 +++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 6eab8a6001db..9cd5c4087c86 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -533,7 +533,6 @@ &pcie_phy {
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
-	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
 		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
@@ -559,6 +558,10 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcie0_port0 {
+	reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+};
+
 &sai2 {
 	#sound-dai-cells = <0>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 9f49c0b386d3..1204cc4d3f37 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1369,6 +1369,17 @@ pcie0: pcie@33800000 {
 			phys = <&pcie_phy>;
 			phy-names = "pcie-phy";
 			status = "disabled";
+
+			pcie0_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie0_ep: pcie-ep@33800000 {
-- 
2.37.1

[PATCH 07/10] arm64: dts: imx8mp: Add Root Port node and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts |  5 ++++-
 arch/arm64/boot/dts/freescale/imx8mp.dtsi    | 11 +++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index b256be710ea1..5d98cf27f1a0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -762,7 +762,6 @@ &pcie_phy {
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
-	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie0>;
 	vpcie3v3aux-supply = <&reg_pcie0>;
 	supports-clkreq;
@@ -775,6 +774,10 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcie0_port0 {
+	reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+};
+
 &pwm1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9b2b3a9bf9e8..f66667735a02 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2266,6 +2266,17 @@ pcie0: pcie: pcie@33800000 {
 			phys = <&pcie_phy>;
 			phy-names = "pcie-phy";
 			status = "disabled";
+
+			pcie0_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie0_ep: pcie_ep: pcie-ep@33800000 {
-- 
2.37.1

[PATCH 08/10] arm64: dts: imx8mq: Add Root Port nodes and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port nodes and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 +++++++--
 arch/arm64/boot/dts/freescale/imx8mq.dtsi    | 22 ++++++++++++++++++++
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index d48f901487d4..723b34100a61 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -369,7 +369,6 @@ mipi_dsi_out: endpoint {
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
-	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
@@ -389,10 +388,13 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcie0_port0 {
+	reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+};
+
 &pcie1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie1>;
-	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
 		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
@@ -414,6 +416,10 @@ &pcie1_ep {
 	status = "disabled";
 };
 
+&pcie1_port0 {
+	reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+};
+
 &pgc_gpu {
 	power-supply = <&sw1a_reg>;
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 607962f807be..de2ba4ee9da6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1768,6 +1768,17 @@ pcie0: pcie@33800000 {
 			assigned-clock-rates = <250000000>, <100000000>,
 			                       <10000000>;
 			status = "disabled";
+
+			pcie0_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie0_ep: pcie-ep@33800000 {
@@ -1846,6 +1857,17 @@ pcie1: pcie@33c00000 {
 			assigned-clock-rates = <250000000>, <100000000>,
 			                       <10000000>;
 			status = "disabled";
+
+			pcie1_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie1_ep: pcie-ep@33c00000 {
-- 
2.37.1

[PATCH 09/10] arm64: dts: imx8dxl/qm/qxp: Add Root Port nodes and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port nodes and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 .../boot/dts/freescale/imx8-ss-hsio.dtsi      | 11 ++++++++++
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts |  5 ++++-
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts  | 10 +++++++--
 .../boot/dts/freescale/imx8qm-ss-hsio.dtsi    | 22 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts |  5 ++++-
 5 files changed, 49 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index 469de8b536b5..009990b2e559 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {
 		power-domains = <&pd IMX_SC_R_PCIE_B>;
 		fsl,max-link-speed = <3>;
 		status = "disabled";
+
+		pcieb_port0: pcie@0 {
+			compatible = "pciclass,0604";
+			device_type = "pci";
+			reg = <0x0 0x0 0x0 0x0 0x0>;
+			bus-range = <0x01 0xff>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+		};
 	};
 
 	pcieb_ep: pcie-ep@5f010000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 5c68d33e19f2..63a655399888 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -651,7 +651,6 @@ &pcie0 {
 	phy-names = "pcie-phy";
 	pinctrl-0 = <&pinctrl_pcieb>;
 	pinctrl-names = "default";
-	reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcieb>;
 	vpcie3v3aux-supply = <&reg_pcieb>;
 	status = "okay";
@@ -667,6 +666,10 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcieb_port0 {
+	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
 &sai0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dadc136aec6e..f57d2391b0ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -802,22 +802,28 @@ &pciea {
 	phy-names = "pcie-phy";
 	pinctrl-0 = <&pinctrl_pciea>;
 	pinctrl-names = "default";
-	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pciea>;
 	vpcie3v3aux-supply = <&reg_pciea>;
 	supports-clkreq;
 	status = "okay";
 };
 
+&pciea_port0 {
+	reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+};
+
 &pcieb {
 	phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
 	phy-names = "pcie-phy";
 	pinctrl-0 = <&pinctrl_pcieb>;
 	pinctrl-names = "default";
-	reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
 	status = "disabled";
 };
 
+&pcieb_port0 {
+	reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
+};
+
 &qm_pwm_lvds0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm_lvds0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index bd6e0aa27efe..48c29c2cfe8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -40,6 +40,17 @@ pcie0: pciea: pcie@5f000000 {
 		power-domains = <&pd IMX_SC_R_PCIE_A>;
 		fsl,max-link-speed = <3>;
 		status = "disabled";
+
+		pciea_port0: pcie@0 {
+			compatible = "pciclass,0604";
+			device_type = "pci";
+			reg = <0x0 0x0 0x0 0x0 0x0>;
+			bus-range = <0x01 0xff>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+		};
 	};
 
 	pcie0_ep: pciea_ep: pcie-ep@5f000000 {
@@ -90,6 +101,17 @@ pcie1: pcieb: pcie@5f010000 {
 		power-domains = <&pd IMX_SC_R_PCIE_B>;
 		fsl,max-link-speed = <3>;
 		status = "disabled";
+
+		pcieb_port0: pcie@0 {
+			compatible = "pciclass,0604";
+			device_type = "pci";
+			reg = <0x0 0x0 0x0 0x0 0x0>;
+			bus-range = <0x01 0xff>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+		};
 	};
 
 	sata: sata@5f020000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 40a0bc9f4e84..fdd9009a2a7e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -722,7 +722,6 @@ &pcie0 {
 	phy-names = "pcie-phy";
 	pinctrl-0 = <&pinctrl_pcieb>;
 	pinctrl-names = "default";
-	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcieb>;
 	vpcie3v3aux-supply = <&reg_pcieb>;
 	supports-clkreq;
@@ -738,6 +737,10 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcieb_port0 {
+	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
 &scu_key {
 	status = "okay";
 };
-- 
2.37.1

[PATCH 10/10] arm64: dts: imx95: Add Root Port nodes and move PERST property to Root Port node

[Sherry Sun]

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port nodes and move the reset-gpios property.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 .../boot/dts/freescale/imx95-15x15-evk.dts    |  5 ++++-
 .../boot/dts/freescale/imx95-19x19-evk.dts    | 10 +++++++--
 arch/arm64/boot/dts/freescale/imx95.dtsi      | 22 +++++++++++++++++++
 3 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index d4184fb8b28c..0f4e45bb1c4a 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -554,7 +554,6 @@ &netcmix_blk_ctrl {
 &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	pinctrl-names = "default";
-	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_m2_pwr>;
 	vpcie3v3aux-supply = <&reg_m2_pwr>;
 	supports-clkreq;
@@ -568,6 +567,10 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcie0_port0 {
+	reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+};
+
 &sai1 {
 	assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
 			  <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index aaa0da55a22b..7d16778f8d49 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -540,7 +540,6 @@ &netc_timer {
 &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	pinctrl-names = "default";
-	reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie0>;
 	vpcie3v3aux-supply = <&reg_pcie0>;
 	supports-clkreq;
@@ -554,10 +553,13 @@ &pcie0_ep {
 	status = "disabled";
 };
 
+&pcie0_port0 {
+	reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
+};
+
 &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	pinctrl-names = "default";
-	reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_slot_pwr>;
 	vpcie3v3aux-supply = <&reg_slot_pwr>;
 	status = "okay";
@@ -570,6 +572,10 @@ &pcie1_ep {
 	status = "disabled";
 };
 
+&pcie1_port0 {
+	reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
+};
+
 &sai1 {
 	#sound-dai-cells = <0>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index a4d854817559..0d5f20b8a42a 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1883,6 +1883,17 @@ pcie0: pcie@4c300000 {
 			iommu-map-mask = <0x1ff>;
 			fsl,max-link-speed = <3>;
 			status = "disabled";
+
+			pcie0_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie0_ep: pcie-ep@4c300000 {
@@ -1960,6 +1971,17 @@ pcie1: pcie@4c380000 {
 			iommu-map-mask = <0x1ff>;
 			fsl,max-link-speed = <3>;
 			status = "disabled";
+
+			pcie1_port0: pcie@0 {
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie1_ep: pcie-ep@4c380000 {
-- 
2.37.1

Re: [PATCH 00/10] pci-imx6: Add support for parsing the reset property in new Root Port binding

[Bjorn Helgaas]

On Mon, Jan 19, 2026 at 06:02:25PM +0800, Sherry Sun wrote:
> This patch set adds support for parsing the reset property in new Root Port
> binding in pci-imx6 driver, similar to the implementation in the qcom pcie
> driver[1].
> 
> The plan is to add the wake-gpio property to the root port in subsequent
> patches. Also, the vpcie-supply property will be moved to the root port
> node later based on the refactoring patch set for the PCI pwrctrl
> framework[2]. 
> 
> [1] https://lore.kernel.org/linux-pci/20250702-perst-v5-0-920b3d1f6ee1@qti.qualcomm.com/
> [2] https://lore.kernel.org/linux-pci/20260115-pci-pwrctrl-rework-v5-0-9d26da3ce903@oss.qualcomm.com/

Is there value in doing this?  It looks like it might be making work
for no benefit.

Certainly for *new* drivers and DTs, we should put resets in the Root
Port.  But this looks like you're moving them in existing DTs.  In
that case, you still have to support the old DTs where the resets are
in the host bridge.

If you are adding support for hardware that has multiple Root Ports
with separate resets for each Root Port, then of course you would need
to put the reset info in per-Root Port stanzas and make changes to
support that, but this series doesn't mention anything about multiple
Root Ports.

> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> Sherry Sun (10):
>   dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
>   PCI: imx6: Add support for parsing the reset property in new Root Port
>     binding
>   arm: dts: imx6qdl: Add Root Port node and move PERST property to Root
>     Port node
>   arm: dts: imx6sx: Add Root Port node and move PERST property to Root
>     Port node
>   arm: dts: imx7d: Add Root Port node and move PERST property to Root
>     Port node
>   arm64: dts: imx8mm: Add Root Port node and move PERST property to Root
>     Port node
>   arm64: dts: imx8mp: Add Root Port node and move PERST property to Root
>     Port node
>   arm64: dts: imx8mq: Add Root Port nodes and move PERST property to
>     Root Port node
>   arm64: dts: imx8dxl/qm/qxp: Add Root Port nodes and move PERST
>     property to Root Port node
>   arm64: dts: imx95: Add Root Port nodes and move PERST property to Root
>     Port node
> 
>  .../bindings/pci/fsl,imx6q-pcie.yaml          |  29 ++++
>  .../arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |   5 +-
>  arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi        |  11 ++
>  .../arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |   5 +-
>  arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi     |   5 +-
>  arch/arm/boot/dts/nxp/imx/imx6sx.dtsi         |  11 ++
>  arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts       |   5 +-
>  arch/arm/boot/dts/nxp/imx/imx7d.dtsi          |  11 ++
>  .../boot/dts/freescale/imx8-ss-hsio.dtsi      |  11 ++
>  arch/arm64/boot/dts/freescale/imx8dxl-evk.dts |   5 +-
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |   5 +-
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  11 ++
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts  |   5 +-
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     |  11 ++
>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts  |  10 +-
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi     |  22 +++
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts  |  10 +-
>  .../boot/dts/freescale/imx8qm-ss-hsio.dtsi    |  22 +++
>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts |   5 +-
>  .../boot/dts/freescale/imx95-15x15-evk.dts    |   5 +-
>  .../boot/dts/freescale/imx95-19x19-evk.dts    |  10 +-
>  arch/arm64/boot/dts/freescale/imx95.dtsi      |  22 +++
>  drivers/pci/controller/dwc/pci-imx6.c         | 128 ++++++++++++++++--
>  23 files changed, 335 insertions(+), 29 deletions(-)
> 
> -- 
> 2.37.1
> 

RE: [PATCH 00/10] pci-imx6: Add support for parsing the reset property in new Root Port binding

[Sherry Sun]

> On Mon, Jan 19, 2026 at 06:02:25PM +0800, Sherry Sun wrote:
> > This patch set adds support for parsing the reset property in new Root
> > Port binding in pci-imx6 driver, similar to the implementation in the
> > qcom pcie driver[1].
> >
> > The plan is to add the wake-gpio property to the root port in
> > subsequent patches. Also, the vpcie-supply property will be moved to
> > the root port node later based on the refactoring patch set for the
> > PCI pwrctrl framework[2].
> >
> > [1]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Flinux-pci%2F20250702-perst-v5-0-920b3d1f6ee1%40qti.qualc
> >
> omm.com%2F&data=05%7C02%7Csherry.sun%40nxp.com%7C7e8defdd9684
> 411f0ee20
> >
> 8de5941a677%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63904
> 63356634
> >
> 52311%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiI
> wLjAuMDAw
> >
> MCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C
> &sdat
> > a=jkm1JxVpIexu05qQIuwV69BTz0xIZOvpRbD3Uv7y414%3D&reserved=0
> > [2]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Flinux-pci%2F20260115-pci-pwrctrl-rework-v5-0-9d26da3ce90
> >
> 3%40oss.qualcomm.com%2F&data=05%7C02%7Csherry.sun%40nxp.com%7C
> 7e8defdd
> >
> 9684411f0ee208de5941a677%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C
> >
> 639046335663465203%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOn
> RydWUsIlY
> >
> iOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%
> 7C0%
> >
> 7C%7C%7C&sdata=YADwJTrzP8fhUR1zacByB1ii9Zl8NlISPINhs0WRmQs%3D&re
> served
> > =0
> 
> Is there value in doing this?  It looks like it might be making work for no
> benefit.
> 
> Certainly for *new* drivers and DTs, we should put resets in the Root Port.
> But this looks like you're moving them in existing DTs.  In that case, you still
> have to support the old DTs where the resets are in the host bridge.
> 
> If you are adding support for hardware that has multiple Root Ports with
> separate resets for each Root Port, then of course you would need to put the
> reset info in per-Root Port stanzas and make changes to support that, but this
> series doesn't mention anything about multiple Root Ports.

Hi Bjorn,
The initial idea is to adopt the Manivannan’s recent PCIe M.2 Key‑E connector
support patch set [3] and PCI power control framework patches, and extend them
to the pcie‑imx6 driver. Since the new M.2/pwrctrl model is implemented based
on Root Ports and requires the pwrctrl driver to bind to a Root Port device, we
need to introduce a Root Port child node on i.MX boards that provide an M.2
connector.

To follow a more standardized DT structure, I believe it also makes sense to move
the reset-gpios and wake-gpios properties into the Root Port node. These signals
logically belong to the Root Port rather than the host bridge, and placing them
there aligns with the new M.2/pwrctrl model.

Regarding backward compatibility, as Frank suggested, I will not remove the old
reset-gpio property from existing DTS files to avoid function break. As for
whether we should backfill Root Port nodes for older DTS files, I don't have a
definitive opinion yet, hope your suggestions.

For new i.MX platforms—such as the upcoming i.MX952—we will add
vpcie-supply, reset-gpios, and wake-gpios directly under the Root Port node.
Therefore, driver updates are needed to support both the legacy properties
and the new standardized Root Port‑based layout.

[3] https://lore.kernel.org/linux-pci/20260112-pci-m2-e-v4-0-eff84d2c6d26@oss.qualcomm.com/

Best Regards
Sherry

> 
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > Sherry Sun (10):
> >   dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
> >   PCI: imx6: Add support for parsing the reset property in new Root Port
> >     binding
> >   arm: dts: imx6qdl: Add Root Port node and move PERST property to Root
> >     Port node
> >   arm: dts: imx6sx: Add Root Port node and move PERST property to Root
> >     Port node
> >   arm: dts: imx7d: Add Root Port node and move PERST property to Root
> >     Port node
> >   arm64: dts: imx8mm: Add Root Port node and move PERST property to
> Root
> >     Port node
> >   arm64: dts: imx8mp: Add Root Port node and move PERST property to
> Root
> >     Port node
> >   arm64: dts: imx8mq: Add Root Port nodes and move PERST property to
> >     Root Port node
> >   arm64: dts: imx8dxl/qm/qxp: Add Root Port nodes and move PERST
> >     property to Root Port node
> >   arm64: dts: imx95: Add Root Port nodes and move PERST property to Root
> >     Port node
> >
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          |  29 ++++
> >  .../arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi |   5 +-
> >  arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi        |  11 ++
> >  .../arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts |   5 +-
> >  arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi     |   5 +-
> >  arch/arm/boot/dts/nxp/imx/imx6sx.dtsi         |  11 ++
> >  arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts       |   5 +-
> >  arch/arm/boot/dts/nxp/imx/imx7d.dtsi          |  11 ++
> >  .../boot/dts/freescale/imx8-ss-hsio.dtsi      |  11 ++
> >  arch/arm64/boot/dts/freescale/imx8dxl-evk.dts |   5 +-
> >  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |   5 +-
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  11 ++
> >  arch/arm64/boot/dts/freescale/imx8mp-evk.dts  |   5 +-
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     |  11 ++
> >  arch/arm64/boot/dts/freescale/imx8mq-evk.dts  |  10 +-
> >  arch/arm64/boot/dts/freescale/imx8mq.dtsi     |  22 +++
> >  arch/arm64/boot/dts/freescale/imx8qm-mek.dts  |  10 +-
> >  .../boot/dts/freescale/imx8qm-ss-hsio.dtsi    |  22 +++
> >  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts |   5 +-
> >  .../boot/dts/freescale/imx95-15x15-evk.dts    |   5 +-
> >  .../boot/dts/freescale/imx95-19x19-evk.dts    |  10 +-
> >  arch/arm64/boot/dts/freescale/imx95.dtsi      |  22 +++
> >  drivers/pci/controller/dwc/pci-imx6.c         | 128 ++++++++++++++++--
> >  23 files changed, 335 insertions(+), 29 deletions(-)
> >
> > --
> > 2.37.1
> >