From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73D2A330B3E; Thu, 22 Jan 2026 23:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769124101; cv=none; b=knn1tHBe0n7mlrjrHePi0pQhoz/DvdmMa4AyN5pIZGIo6J7Z4SouLCNRg18hXgIi5ggpuF8+CxquJzsZthU2mEn/HgHRQ09hpcsA4yxqlXhxOSTNLV9xk8mCCaG85OUfHa/Q1PVAzaFw6xrPUqCXNu/dlqd/b22kwflV0E5SyOM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769124101; c=relaxed/simple; bh=vUOqLJV03qwaBfmuHwqXoOQ/IdKsiWbk/K4GdntR+BM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bwX/kvxEIJIF4Dx1q2walqEhc+7VE9KeGl3rW2xKObYuNMkHS+gQPcdhefKPpID4Taf+W0FgoHZnn/1sr3SLRz4up15fGkxYAEu/GGVG48TFqTv0rNtiP3GM66tEQ5pv01PLhzJ+wCudB9181XL32/L+xP6CmP/JXKdJ8/eJwAQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lekxa4Nh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lekxa4Nh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D927C116C6; Thu, 22 Jan 2026 23:21:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769124100; bh=vUOqLJV03qwaBfmuHwqXoOQ/IdKsiWbk/K4GdntR+BM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lekxa4NhA2b+jIufWjek4xt/AQ3UGxjRXVopuVx1/yJ3TyznR95IhK28K94qlOC/r tpV6+BC7k9LYA8mY2TdXOpSrt2T0yF+mJTw6i8m2OHig9F1tS3l/Sk1L/d0cVM0CVt oK74KFnQgA5DDSTwKyG74sZTZ+wce0e/PocViI6eAvbGwbtrSlqbsIqD71V5IjQOLA dv9AKO58oxXnJ+aiqVLuWEyt0KUrdvfIL4tKzqm/6uw++PY4MUC4yHtMwZmW0A5z9+ ui5GBZeoi2YRPwQBZUkLHTD6I2D/AjciWG+/gVNRAsDgxex/iI5ywdTjUUuv4Fka8/ TfVxHvjFAtCKw== Date: Thu, 22 Jan 2026 17:21:39 -0600 From: Rob Herring To: Gatien CHEVALLIER Cc: Suzuki K Poulose , Mike Leach , James Clark , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , =?iso-8859-1?Q?Cl=E9ment?= Le Goffic , Linus Walleij , Maxime Coquelin , Alexandre Torgue , jens.wiklander@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: Re: [PATCH v4 03/12] dt-bindings: bus: document the stm32 debug bus Message-ID: <20260122232139.GA3717629-robh@kernel.org> References: <20260122-debug_bus-v4-0-28f0f2a25f2c@foss.st.com> <20260122-debug_bus-v4-3-28f0f2a25f2c@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Jan 22, 2026 at 05:22:21PM +0100, Gatien CHEVALLIER wrote: > > > On 1/22/26 17:19, Gatien Chevallier wrote: > > Document the stm32 debug bus. The debug bus is responsible for > > checking the debug sub-system accessibility before probing any related > > drivers. > > > > Signed-off-by: Gatien Chevallier > > --- > > .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 77 ++++++++++++++++++++++ > > 1 file changed, 77 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml > > new file mode 100644 > > index 000000000000..57f01d301e75 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: STM32 Coresight bus > > + > > +maintainers: > > + - Gatien Chevallier > > + > > +description: > > + The STM32 debug bus is in charge of checking the debug configuration > > + of the platform before probing the peripheral drivers that rely on the debug > > + domain. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - st,stm32mp131-dbg-bus > > + - st,stm32mp151-dbg-bus > > + > > + "#address-cells": > > + const: 1 > > + > > + "#size-cells": > > + const: 1 > > + > > + ranges: true > > Maybe maxItems:2 is preferred here, no? Wouldn't it be 1 as there is only 1 range? Up to you whether you want to limit it or not. > > > + > > + reg: > > + maxItems: 1 Should be dropped? > > + > > + "#access-controller-cells": > > + const: 1 > > + description: > > + Contains the debug profile necessary to access the peripheral. > > + > > +patternProperties: > > + "^.*@[0-9a-f]+$": This can be: "@[0-9a-f]+$" > > + description: Debug related peripherals > > + type: object > > + > > + additionalProperties: true > > + > > + required: > > + - access-controllers > > + > > +required: > > + - "#access-controller-cells" > > + - "#address-cells" > > + - "#size-cells" > > + - compatible > > + - ranges > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + > > + dbg_bus: bus@50080000 { Drop unused labels. > > + compatible = "st,stm32mp131-dbg-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + #access-controller-cells = <1>; > > + ranges = <0x50080000 0x50080000 0x3f80000>; > > + > > + cs_cti_trace: cti@50094000 { > > + compatible = "arm,coresight-cti", "arm,primecell"; > > + reg = <0x50094000 0x1000>; > > + clocks = <&rcc CK_DBG>; > > + clock-names = "apb_pclk"; > > + access-controllers = <&dbg_bus 0>; > > + }; > > + }; > > >