* [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC
@ 2026-01-20 11:10 Guodong Xu
2026-01-20 11:10 ` [PATCH v3 1/4] dt-bindings: soc: spacemit: Add K3 reset support and IDs Guodong Xu
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Guodong Xu @ 2026-01-20 11:10 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu
Cc: Alex Elder, linux-kernel, devicetree, linux-riscv, spacemit,
Guodong Xu, Krzysztof Kozlowski
This series adds support for the reset controller found on the SpacemiT
K3 SoC.
The clock driver changes, which defined new auxiliary device name
patterns for reset on K1 and K3, have been applied to the clock tree.
To facilitate merging, Yixun Lan has created an immutable tag
(spacemit-clkrst-v6.20-3) within his pull request to the clock
subsystem [1]. Hence, the dependencies mentioned in v2 have now
been deblocked, making the reset driver ready to be applied, if it
gets approval from review.
In this version (v3), the entire series has been rebased and tested
on top of the linux-next tag: next-20260119.
General informaiton about the series:
The K3 reset controller shares the same architecture as the K1. To
facilitate support for both and future SoCs, the existing K1 reset
driver is refactored with the following changes:
1. The existing K1 driver is moved to a dedicated 'drivers/reset/spacemit/'
directory.
2. Common reset operations are extracted into reset-spacemit-common.{c,h}
The K3 driver is implemented using this common infrastructure.
Link: https://lore.kernel.org/linux-clk/20260114060410.3340540-1-yixun.lan@gmail.com/ [1]
Changes in v3:
- Updated dependency status and base information.
- Patch 1:
Add Acked-by from Krzysztof and Alex.
- Patch 2:
Removed trailing blank line from Makefile.
- Patch 1/2/3/4:
Add Acked-by / Reviewed-by from Alex Elder.
- Link to v2: https://lore.kernel.org/r/20260108-k3-reset-v2-0-457df235efe9@riscstar.com
Changes in v2:
- Patch 1:
Update the commit message to explain the why.
Update the spacemit,k1-syscon.yaml to point to k3 reset IDs
header file.
- Patch 3:
Use dev->driver->owner for the reset controller owner instead of
THIS_MODULE to fix the module reference counting issue pointed out
by Krzysztof Kozlowski.
- Patch 3 and 4:
Update the K1_AUX_DEV_ID and K3_AUX_DEV_ID macros to a simpler but direct
form, one benefit is to improve the code readability. More discussion
can be found in Link [4].
Link to v1: https://lore.kernel.org/r/20251229-k3-reset-v1-0-eda0747bded3@riscstar.com
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Guodong Xu (4):
dt-bindings: soc: spacemit: Add K3 reset support and IDs
reset: Create subdirectory for SpacemiT drivers
reset: spacemit: Extract common K1 reset code
reset: spacemit: Add SpacemiT K3 reset driver
.../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 8 +-
drivers/reset/Kconfig | 12 +-
drivers/reset/Makefile | 2 +-
drivers/reset/spacemit/Kconfig | 36 ++++
drivers/reset/spacemit/Makefile | 5 +
drivers/reset/spacemit/reset-spacemit-common.c | 77 +++++++
drivers/reset/spacemit/reset-spacemit-common.h | 42 ++++
.../reset-spacemit-k1.c} | 107 +---------
drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++
include/dt-bindings/reset/spacemit,k3-resets.h | 171 +++++++++++++++
10 files changed, 583 insertions(+), 110 deletions(-)
---
base-commit: 6ada99659c6d6a0cde83e6c0f4ed0ef0ba1867e1
change-id: 20251229-k3-reset-8d9b751ef391
Best regards,
--
Guodong Xu <guodong@riscstar.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 1/4] dt-bindings: soc: spacemit: Add K3 reset support and IDs
2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
@ 2026-01-20 11:10 ` Guodong Xu
2026-01-20 11:10 ` [PATCH v3 2/4] reset: Create subdirectory for SpacemiT drivers Guodong Xu
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Guodong Xu @ 2026-01-20 11:10 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu
Cc: Alex Elder, linux-kernel, devicetree, linux-riscv, spacemit,
Guodong Xu, Krzysztof Kozlowski
Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset
support.
K3 reset devices are registered at runtime as auxiliary devices by the
K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate
YAML binding file for K3 resets.
Update #reset-cells description to document where reset IDs are defined.
Acked-by: Alex Elder <elder@riscstar.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v3: Add Acked-by from Krzysztof and Alex.
v2: Update spacemit,k1-syscon binding to clarify K3 reset is supported.
Update the commit message to add backgrounds of this patch why,
instead of what.
---
.../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 8 +-
include/dt-bindings/reset/spacemit,k3-resets.h | 171 +++++++++++++++++++++
2 files changed, 178 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
index 66e6683a3ccb..1a28af22cac1 100644
--- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
@@ -10,7 +10,7 @@ maintainers:
- Haylen Chu <heylenay@4d2.org>
description:
- System controllers found on SpacemiT K1 SoC, which are capable of
+ System controllers found on SpacemiT K1/K3 SoC, which are capable of
clock, reset and power-management functions.
properties:
@@ -50,6 +50,12 @@ properties:
"#reset-cells":
const: 1
+ description: |
+ ID of the reset controller line. Valid IDs are defined in corresponding
+ files:
+
+ For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h
+ For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h
required:
- compatible
diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
new file mode 100644
index 000000000000..79ac1c22b7b5
--- /dev/null
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
+#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
+
+/* MPMU resets */
+#define RESET_MPMU_WDT 0
+#define RESET_MPMU_RIPC 1
+
+/* APBC resets */
+#define RESET_APBC_UART0 0
+#define RESET_APBC_UART2 1
+#define RESET_APBC_UART3 2
+#define RESET_APBC_UART4 3
+#define RESET_APBC_UART5 4
+#define RESET_APBC_UART6 5
+#define RESET_APBC_UART7 6
+#define RESET_APBC_UART8 7
+#define RESET_APBC_UART9 8
+#define RESET_APBC_UART10 9
+#define RESET_APBC_GPIO 10
+#define RESET_APBC_PWM0 11
+#define RESET_APBC_PWM1 12
+#define RESET_APBC_PWM2 13
+#define RESET_APBC_PWM3 14
+#define RESET_APBC_PWM4 15
+#define RESET_APBC_PWM5 16
+#define RESET_APBC_PWM6 17
+#define RESET_APBC_PWM7 18
+#define RESET_APBC_PWM8 19
+#define RESET_APBC_PWM9 20
+#define RESET_APBC_PWM10 21
+#define RESET_APBC_PWM11 22
+#define RESET_APBC_PWM12 23
+#define RESET_APBC_PWM13 24
+#define RESET_APBC_PWM14 25
+#define RESET_APBC_PWM15 26
+#define RESET_APBC_PWM16 27
+#define RESET_APBC_PWM17 28
+#define RESET_APBC_PWM18 29
+#define RESET_APBC_PWM19 30
+#define RESET_APBC_SPI0 31
+#define RESET_APBC_SPI1 32
+#define RESET_APBC_SPI3 33
+#define RESET_APBC_RTC 34
+#define RESET_APBC_TWSI0 35
+#define RESET_APBC_TWSI1 36
+#define RESET_APBC_TWSI2 37
+#define RESET_APBC_TWSI4 38
+#define RESET_APBC_TWSI5 39
+#define RESET_APBC_TWSI6 40
+#define RESET_APBC_TWSI8 41
+#define RESET_APBC_TIMERS0 42
+#define RESET_APBC_TIMERS1 43
+#define RESET_APBC_TIMERS2 44
+#define RESET_APBC_TIMERS3 45
+#define RESET_APBC_TIMERS4 46
+#define RESET_APBC_TIMERS5 47
+#define RESET_APBC_TIMERS6 48
+#define RESET_APBC_TIMERS7 49
+#define RESET_APBC_AIB 50
+#define RESET_APBC_ONEWIRE 51
+#define RESET_APBC_I2S0 52
+#define RESET_APBC_I2S1 53
+#define RESET_APBC_I2S2 54
+#define RESET_APBC_I2S3 55
+#define RESET_APBC_I2S4 56
+#define RESET_APBC_I2S5 57
+#define RESET_APBC_DRO 58
+#define RESET_APBC_IR0 59
+#define RESET_APBC_IR1 60
+#define RESET_APBC_TSEN 61
+#define RESET_IPC_AP2AUD 62
+#define RESET_APBC_CAN0 63
+#define RESET_APBC_CAN1 64
+#define RESET_APBC_CAN2 65
+#define RESET_APBC_CAN3 66
+#define RESET_APBC_CAN4 67
+
+/* APMU resets */
+#define RESET_APMU_CSI 0
+#define RESET_APMU_CCIC2PHY 1
+#define RESET_APMU_CCIC3PHY 2
+#define RESET_APMU_ISP_CIBUS 3
+#define RESET_APMU_DSI_ESC 4
+#define RESET_APMU_LCD 5
+#define RESET_APMU_V2D 6
+#define RESET_APMU_LCD_MCLK 7
+#define RESET_APMU_LCD_DSCCLK 8
+#define RESET_APMU_SC2_HCLK 9
+#define RESET_APMU_CCIC_4X 10
+#define RESET_APMU_CCIC1_PHY 11
+#define RESET_APMU_SDH_AXI 12
+#define RESET_APMU_SDH0 13
+#define RESET_APMU_SDH1 14
+#define RESET_APMU_SDH2 15
+#define RESET_APMU_USB2 16
+#define RESET_APMU_USB3_PORTA 17
+#define RESET_APMU_USB3_PORTB 18
+#define RESET_APMU_USB3_PORTC 19
+#define RESET_APMU_USB3_PORTD 20
+#define RESET_APMU_QSPI 21
+#define RESET_APMU_QSPI_BUS 22
+#define RESET_APMU_DMA 23
+#define RESET_APMU_AES_WTM 24
+#define RESET_APMU_MCB_DCLK 25
+#define RESET_APMU_MCB_ACLK 26
+#define RESET_APMU_VPU 27
+#define RESET_APMU_DTC 28
+#define RESET_APMU_GPU 29
+#define RESET_APMU_ALZO 30
+#define RESET_APMU_MC 31
+#define RESET_APMU_CPU0_POP 32
+#define RESET_APMU_CPU0_SW 33
+#define RESET_APMU_CPU1_POP 34
+#define RESET_APMU_CPU1_SW 35
+#define RESET_APMU_CPU2_POP 36
+#define RESET_APMU_CPU2_SW 37
+#define RESET_APMU_CPU3_POP 38
+#define RESET_APMU_CPU3_SW 39
+#define RESET_APMU_C0_MPSUB_SW 40
+#define RESET_APMU_CPU4_POP 41
+#define RESET_APMU_CPU4_SW 42
+#define RESET_APMU_CPU5_POP 43
+#define RESET_APMU_CPU5_SW 44
+#define RESET_APMU_CPU6_POP 45
+#define RESET_APMU_CPU6_SW 46
+#define RESET_APMU_CPU7_POP 47
+#define RESET_APMU_CPU7_SW 48
+#define RESET_APMU_C1_MPSUB_SW 49
+#define RESET_APMU_MPSUB_DBG 50
+#define RESET_APMU_UCIE 51
+#define RESET_APMU_RCPU 52
+#define RESET_APMU_DSI4LN2_ESCCLK 53
+#define RESET_APMU_DSI4LN2_LCD_SW 54
+#define RESET_APMU_DSI4LN2_LCD_MCLK 55
+#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56
+#define RESET_APMU_DSI4LN2_DPU_ACLK 57
+#define RESET_APMU_DPU_ACLK 58
+#define RESET_APMU_UFS_ACLK 59
+#define RESET_APMU_EDP0 60
+#define RESET_APMU_EDP1 61
+#define RESET_APMU_PCIE_PORTA 62
+#define RESET_APMU_PCIE_PORTB 63
+#define RESET_APMU_PCIE_PORTC 64
+#define RESET_APMU_PCIE_PORTD 65
+#define RESET_APMU_PCIE_PORTE 66
+#define RESET_APMU_EMAC0 67
+#define RESET_APMU_EMAC1 68
+#define RESET_APMU_EMAC2 69
+#define RESET_APMU_ESPI_MCLK 70
+#define RESET_APMU_ESPI_SCLK 71
+
+/* DCIU resets*/
+#define RESET_DCIU_HDMA 0
+#define RESET_DCIU_DMA350 1
+#define RESET_DCIU_DMA350_0 2
+#define RESET_DCIU_DMA350_1 3
+#define RESET_DCIU_AXIDMA0 4
+#define RESET_DCIU_AXIDMA1 5
+#define RESET_DCIU_AXIDMA2 6
+#define RESET_DCIU_AXIDMA3 7
+#define RESET_DCIU_AXIDMA4 8
+#define RESET_DCIU_AXIDMA5 9
+#define RESET_DCIU_AXIDMA6 10
+#define RESET_DCIU_AXIDMA7 11
+
+#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/4] reset: Create subdirectory for SpacemiT drivers
2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
2026-01-20 11:10 ` [PATCH v3 1/4] dt-bindings: soc: spacemit: Add K3 reset support and IDs Guodong Xu
@ 2026-01-20 11:10 ` Guodong Xu
2026-01-20 11:10 ` [PATCH v3 3/4] reset: spacemit: Extract common K1 reset code Guodong Xu
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Guodong Xu @ 2026-01-20 11:10 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu
Cc: Alex Elder, linux-kernel, devicetree, linux-riscv, spacemit,
Guodong Xu
Create a dedicated subdirectory for SpacemiT reset drivers to allow
for better organization as support for more SoCs is added.
Move the existing K1 reset driver into this new directory and rename
it to reset-spacemit-k1.c.
Rename the Kconfig symbol to RESET_SPACEMIT_K1 and update its default
from ARCH_SPACEMIT to SPACEMIT_K1_CCU. The reset driver depends on the
clock driver to register reset devices as an auxiliary device, so the
default should reflect this dependency.
Also sort the drivers/reset/Kconfig entries alphabetically.
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v3: Add Alex's reviewed-by.
Remove the trailing empty newline in Makefile to keep constant style
with others in the reset folder.
v2: No change.
---
drivers/reset/Kconfig | 12 ++----------
drivers/reset/Makefile | 2 +-
drivers/reset/spacemit/Kconfig | 14 ++++++++++++++
drivers/reset/spacemit/Makefile | 2 ++
.../{reset-spacemit.c => spacemit/reset-spacemit-k1.c} | 0
5 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6e5d6deffa7d..b110f0fa7bb1 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -299,15 +299,6 @@ config RESET_SOCFPGA
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
-config RESET_SPACEMIT
- tristate "SpacemiT reset driver"
- depends on ARCH_SPACEMIT || COMPILE_TEST
- select AUXILIARY_BUS
- default ARCH_SPACEMIT
- help
- This enables the reset controller driver for SpacemiT SoCs,
- including the K1.
-
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS
@@ -406,9 +397,10 @@ config RESET_ZYNQMP
This enables the reset controller driver for Xilinx ZynqMP SoCs.
source "drivers/reset/amlogic/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
+source "drivers/reset/spacemit/Kconfig"
source "drivers/reset/starfive/Kconfig"
source "drivers/reset/sti/Kconfig"
-source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig"
endif
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 9c3e484dfd81..fc0cc99f8514 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -2,6 +2,7 @@
obj-y += core.o
obj-y += amlogic/
obj-y += hisilicon/
+obj-y += spacemit/
obj-y += starfive/
obj-y += sti/
obj-y += tegra/
@@ -38,7 +39,6 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
-obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o
diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig
new file mode 100644
index 000000000000..552884e8b72a
--- /dev/null
+++ b/drivers/reset/spacemit/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config RESET_SPACEMIT_K1
+ tristate "SpacemiT K1 reset driver"
+ depends on ARCH_SPACEMIT || COMPILE_TEST
+ depends on SPACEMIT_K1_CCU
+ select AUXILIARY_BUS
+ default SPACEMIT_K1_CCU
+ help
+ Support for reset controller in SpacemiT K1 SoC.
+ This driver works with the SpacemiT K1 clock controller
+ unit (CCU) driver to provide reset control functionality
+ for various peripherals and subsystems in the SoC.
+
diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile
new file mode 100644
index 000000000000..34e3350136bb
--- /dev/null
+++ b/drivers/reset/spacemit/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/spacemit/reset-spacemit-k1.c
similarity index 100%
rename from drivers/reset/reset-spacemit.c
rename to drivers/reset/spacemit/reset-spacemit-k1.c
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/4] reset: spacemit: Extract common K1 reset code
2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
2026-01-20 11:10 ` [PATCH v3 1/4] dt-bindings: soc: spacemit: Add K3 reset support and IDs Guodong Xu
2026-01-20 11:10 ` [PATCH v3 2/4] reset: Create subdirectory for SpacemiT drivers Guodong Xu
@ 2026-01-20 11:10 ` Guodong Xu
2026-01-20 11:10 ` [PATCH v3 4/4] reset: spacemit: Add SpacemiT K3 reset driver Guodong Xu
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Guodong Xu @ 2026-01-20 11:10 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu
Cc: Alex Elder, linux-kernel, devicetree, linux-riscv, spacemit,
Guodong Xu
Extract the common reset controller code from the K1 driver into
separate reset-spacemit-common.{c,h} files to prepare for additional
SpacemiT SoCs that share the same reset controller architecture.
The common code includes handlers for reset assert and deassert
operations and probing for auxiliary bus devices.
Changes during extraction:
- Module ownership: Use dev->driver->owner instead of THIS_MODULE in
spacemit_reset_controller_register() to correctly reference the
calling driver's module.
- Rename spacemit_reset_ids to spacemit_k1_reset_ids.
- Define new namespace "RESET_SPACEMIT" for the exported common
functions (spacemit_reset_probe) and update K1 driver to import it.
This prepares for additional SpacemiT SoCs (K3) that share the same reset
controller architecture.
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v3: Add reviewed-by from Alex.
v2: Use dev->driver->owner for the reset controller owner instead of
THIS_MODULE to fix the module reference counting issue pointed out
by Krzysztof Kozlowski.
---
drivers/reset/spacemit/Kconfig | 17 +++-
drivers/reset/spacemit/Makefile | 2 +
drivers/reset/spacemit/reset-spacemit-common.c | 77 ++++++++++++++++++
drivers/reset/spacemit/reset-spacemit-common.h | 42 ++++++++++
drivers/reset/spacemit/reset-spacemit-k1.c | 107 +++----------------------
5 files changed, 144 insertions(+), 101 deletions(-)
diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig
index 552884e8b72a..56a4858b30e1 100644
--- a/drivers/reset/spacemit/Kconfig
+++ b/drivers/reset/spacemit/Kconfig
@@ -1,10 +1,20 @@
# SPDX-License-Identifier: GPL-2.0-only
-config RESET_SPACEMIT_K1
- tristate "SpacemiT K1 reset driver"
+menu "Reset support for SpacemiT platforms"
depends on ARCH_SPACEMIT || COMPILE_TEST
- depends on SPACEMIT_K1_CCU
+
+config RESET_SPACEMIT_COMMON
+ tristate
select AUXILIARY_BUS
+ help
+ Common reset controller infrastructure for SpacemiT SoCs.
+ This provides shared code and helper functions used by
+ reset drivers for various SpacemiT SoC families.
+
+config RESET_SPACEMIT_K1
+ tristate "Support for SpacemiT K1 SoC"
+ depends on SPACEMIT_K1_CCU
+ select RESET_SPACEMIT_COMMON
default SPACEMIT_K1_CCU
help
Support for reset controller in SpacemiT K1 SoC.
@@ -12,3 +22,4 @@ config RESET_SPACEMIT_K1
unit (CCU) driver to provide reset control functionality
for various peripherals and subsystems in the SoC.
+endmenu
diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile
index 34e3350136bb..0b056e8661ec 100644
--- a/drivers/reset/spacemit/Makefile
+++ b/drivers/reset/spacemit/Makefile
@@ -1,2 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o
+
obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset/spacemit/reset-spacemit-common.c
new file mode 100644
index 000000000000..0626633a5e7d
--- /dev/null
+++ b/drivers/reset/spacemit/reset-spacemit-common.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* SpacemiT reset controller driver - common implementation */
+
+#include <linux/container_of.h>
+#include <linux/device.h>
+#include <linux/module.h>
+
+#include <soc/spacemit/ccu.h>
+
+#include "reset-spacemit-common.h"
+
+static int spacemit_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct ccu_reset_controller *controller;
+ const struct ccu_reset_data *data;
+ u32 mask;
+ u32 val;
+
+ controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
+ data = &controller->data->reset_data[id];
+ mask = data->assert_mask | data->deassert_mask;
+ val = assert ? data->assert_mask : data->deassert_mask;
+
+ return regmap_update_bits(controller->regmap, data->offset, mask, val);
+}
+
+static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return spacemit_reset_update(rcdev, id, true);
+}
+
+static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return spacemit_reset_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops spacemit_reset_control_ops = {
+ .assert = spacemit_reset_assert,
+ .deassert = spacemit_reset_deassert,
+};
+
+static int spacemit_reset_controller_register(struct device *dev,
+ struct ccu_reset_controller *controller)
+{
+ struct reset_controller_dev *rcdev = &controller->rcdev;
+
+ rcdev->ops = &spacemit_reset_control_ops;
+ rcdev->owner = dev->driver->owner;
+ rcdev->of_node = dev->of_node;
+ rcdev->nr_resets = controller->data->count;
+
+ return devm_reset_controller_register(dev, &controller->rcdev);
+}
+
+int spacemit_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
+ struct ccu_reset_controller *controller;
+ struct device *dev = &adev->dev;
+
+ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
+ if (!controller)
+ return -ENOMEM;
+ controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
+ controller->regmap = rdev->regmap;
+
+ return spacemit_reset_controller_register(dev, controller);
+}
+EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT");
+
+MODULE_DESCRIPTION("SpacemiT reset controller driver - common code");
+MODULE_LICENSE("GPL");
diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset/spacemit/reset-spacemit-common.h
new file mode 100644
index 000000000000..ffaf2f86eb39
--- /dev/null
+++ b/drivers/reset/spacemit/reset-spacemit-common.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * SpacemiT reset controller driver - common definitions
+ */
+
+#ifndef _RESET_SPACEMIT_COMMON_H_
+#define _RESET_SPACEMIT_COMMON_H_
+
+#include <linux/auxiliary_bus.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct ccu_reset_data {
+ u32 offset;
+ u32 assert_mask;
+ u32 deassert_mask;
+};
+
+struct ccu_reset_controller_data {
+ const struct ccu_reset_data *reset_data; /* array */
+ size_t count;
+};
+
+struct ccu_reset_controller {
+ struct reset_controller_dev rcdev;
+ const struct ccu_reset_controller_data *data;
+ struct regmap *regmap;
+};
+
+#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
+ { \
+ .offset = (_offset), \
+ .assert_mask = (_assert_mask), \
+ .deassert_mask = (_deassert_mask), \
+ }
+
+/* Common probe function */
+int spacemit_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id);
+
+#endif /* _RESET_SPACEMIT_COMMON_H_ */
diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c
index cc7fd1f8750d..8f3b5329ea5f 100644
--- a/drivers/reset/spacemit/reset-spacemit-k1.c
+++ b/drivers/reset/spacemit/reset-spacemit-k1.c
@@ -1,41 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* SpacemiT reset controller driver */
+/* SpacemiT K1 reset controller driver */
-#include <linux/auxiliary_bus.h>
-#include <linux/container_of.h>
-#include <linux/device.h>
#include <linux/module.h>
-#include <linux/regmap.h>
-#include <linux/reset-controller.h>
-#include <linux/types.h>
-#include <soc/spacemit/k1-syscon.h>
#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <soc/spacemit/k1-syscon.h>
-struct ccu_reset_data {
- u32 offset;
- u32 assert_mask;
- u32 deassert_mask;
-};
-
-struct ccu_reset_controller_data {
- const struct ccu_reset_data *reset_data; /* array */
- size_t count;
-};
-
-struct ccu_reset_controller {
- struct reset_controller_dev rcdev;
- const struct ccu_reset_controller_data *data;
- struct regmap *regmap;
-};
-
-#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
- { \
- .offset = (_offset), \
- .assert_mask = (_assert_mask), \
- .deassert_mask = (_deassert_mask), \
- }
+#include "reset-spacemit-common.h"
static const struct ccu_reset_data k1_mpmu_resets[] = {
[RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
@@ -214,91 +186,30 @@ static const struct ccu_reset_controller_data k1_apbc2_reset_data = {
.count = ARRAY_SIZE(k1_apbc2_resets),
};
-static int spacemit_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
- struct ccu_reset_controller *controller;
- const struct ccu_reset_data *data;
- u32 mask;
- u32 val;
-
- controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
- data = &controller->data->reset_data[id];
- mask = data->assert_mask | data->deassert_mask;
- val = assert ? data->assert_mask : data->deassert_mask;
-
- return regmap_update_bits(controller->regmap, data->offset, mask, val);
-}
-
-static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return spacemit_reset_update(rcdev, id, true);
-}
-
-static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return spacemit_reset_update(rcdev, id, false);
-}
-
-static const struct reset_control_ops spacemit_reset_control_ops = {
- .assert = spacemit_reset_assert,
- .deassert = spacemit_reset_deassert,
-};
-
-static int spacemit_reset_controller_register(struct device *dev,
- struct ccu_reset_controller *controller)
-{
- struct reset_controller_dev *rcdev = &controller->rcdev;
-
- rcdev->ops = &spacemit_reset_control_ops;
- rcdev->owner = THIS_MODULE;
- rcdev->of_node = dev->of_node;
- rcdev->nr_resets = controller->data->count;
-
- return devm_reset_controller_register(dev, &controller->rcdev);
-}
-
-static int spacemit_reset_probe(struct auxiliary_device *adev,
- const struct auxiliary_device_id *id)
-{
- struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
- struct ccu_reset_controller *controller;
- struct device *dev = &adev->dev;
-
- controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
- if (!controller)
- return -ENOMEM;
- controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
- controller->regmap = rdev->regmap;
-
- return spacemit_reset_controller_register(dev, controller);
-}
-
#define K1_AUX_DEV_ID(_unit) \
{ \
.name = "spacemit_ccu.k1-" #_unit "-reset", \
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
}
-static const struct auxiliary_device_id spacemit_reset_ids[] = {
+static const struct auxiliary_device_id spacemit_k1_reset_ids[] = {
K1_AUX_DEV_ID(mpmu),
K1_AUX_DEV_ID(apbc),
K1_AUX_DEV_ID(apmu),
K1_AUX_DEV_ID(rcpu),
K1_AUX_DEV_ID(rcpu2),
K1_AUX_DEV_ID(apbc2),
- { },
+ { /* sentinel */ }
};
-MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids);
+MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids);
static struct auxiliary_driver spacemit_k1_reset_driver = {
.probe = spacemit_reset_probe,
- .id_table = spacemit_reset_ids,
+ .id_table = spacemit_k1_reset_ids,
};
module_auxiliary_driver(spacemit_k1_reset_driver);
+MODULE_IMPORT_NS("RESET_SPACEMIT");
MODULE_AUTHOR("Alex Elder <elder@kernel.org>");
-MODULE_DESCRIPTION("SpacemiT reset controller driver");
+MODULE_DESCRIPTION("SpacemiT K1 reset controller driver");
MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 4/4] reset: spacemit: Add SpacemiT K3 reset driver
2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
` (2 preceding siblings ...)
2026-01-20 11:10 ` [PATCH v3 3/4] reset: spacemit: Extract common K1 reset code Guodong Xu
@ 2026-01-20 11:10 ` Guodong Xu
2026-01-20 12:19 ` [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
2026-01-23 1:24 ` Yixun Lan
5 siblings, 0 replies; 7+ messages in thread
From: Guodong Xu @ 2026-01-20 11:10 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu
Cc: Alex Elder, linux-kernel, devicetree, linux-riscv, spacemit,
Guodong Xu
Add support for the SpacemiT K3 SoC reset controller. The K3 reset
driver reuses the common reset controller code and provides K3-specific
reset data for devices managed by the following units:
- MPMU (Main Power Management Unit)
- APBC (APB clock unit)
- APMU (Application Subsystem Power Management Unit)
- DCIU (DMA Control and Interface Unit)
Acked-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v3: Add acked-by from Alex.
v2: No change.
---
drivers/reset/spacemit/Kconfig | 11 ++
drivers/reset/spacemit/Makefile | 1 +
drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++++++++++
3 files changed, 245 insertions(+)
diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig
index 56a4858b30e1..545d6b41c6ca 100644
--- a/drivers/reset/spacemit/Kconfig
+++ b/drivers/reset/spacemit/Kconfig
@@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1
unit (CCU) driver to provide reset control functionality
for various peripherals and subsystems in the SoC.
+config RESET_SPACEMIT_K3
+ tristate "Support for SpacemiT K3 SoC"
+ depends on SPACEMIT_K3_CCU
+ select RESET_SPACEMIT_COMMON
+ default SPACEMIT_K3_CCU
+ help
+ Support for reset controller in SpacemiT K3 SoC.
+ This driver works with the SpacemiT K3 clock controller
+ unit (CCU) driver to provide reset control functionality
+ for various peripherals and subsystems in the SoC.
+
endmenu
diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile
index 0b056e8661ec..00669132c6ac 100644
--- a/drivers/reset/spacemit/Makefile
+++ b/drivers/reset/spacemit/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o
obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
+obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o
diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c
new file mode 100644
index 000000000000..e9e32e4c1ba5
--- /dev/null
+++ b/drivers/reset/spacemit/reset-spacemit-k3.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* SpacemiT K3 reset controller driver */
+
+#include <linux/module.h>
+
+#include <dt-bindings/reset/spacemit,k3-resets.h>
+#include <soc/spacemit/k3-syscon.h>
+
+#include "reset-spacemit-common.h"
+
+static const struct ccu_reset_data k3_mpmu_resets[] = {
+ [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
+ [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0),
+};
+
+static const struct ccu_reset_controller_data k3_mpmu_reset_data = {
+ .reset_data = k3_mpmu_resets,
+ .count = ARRAY_SIZE(k3_mpmu_resets),
+};
+
+static const struct ccu_reset_data k3_apbc_resets[] = {
+ [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
+ [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0),
+ [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0),
+ [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0),
+ [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
+ [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0),
+ [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
+ [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
+ [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0),
+ [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0),
+ [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0),
+ [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0),
+ [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
+ [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
+ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
+ [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
+ [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0),
+ [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0),
+ [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0),
+ [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0),
+};
+
+static const struct ccu_reset_controller_data k3_apbc_reset_data = {
+ .reset_data = k3_apbc_resets,
+ .count = ARRAY_SIZE(k3_apbc_resets),
+};
+
+static const struct ccu_reset_data k3_apmu_resets[] = {
+ [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
+ [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
+ [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
+ [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
+ [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
+ [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
+ [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
+ [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)),
+ [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
+ [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(1)|BIT(2)|BIT(3)),
+ [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(5)|BIT(6)|BIT(7)),
+ [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(9)|BIT(10)|BIT(11)),
+ [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(13)|BIT(14)|BIT(15)),
+ [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
+ BIT(17)|BIT(18)|BIT(19)),
+ [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
+ [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
+ [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0),
+ [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0),
+ [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0),
+ [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0),
+ [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0),
+ [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0),
+ [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0),
+ [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0),
+ [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0),
+ [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0),
+ [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0),
+ [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0),
+ [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0),
+ [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0),
+ [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0),
+ [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0),
+ [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0),
+ [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0),
+ [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0),
+ [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL,
+ BIT(1) | BIT(2) | BIT(3), 0),
+ [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0,
+ BIT(3) | BIT(2) | BIT(0)),
+ [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)),
+ [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)),
+ [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)),
+ [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)),
+ [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)),
+ [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)),
+ [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)),
+ [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)),
+ [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0,
+ BIT(5) | BIT(4) | BIT(3)),
+ [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0,
+ BIT(5) | BIT(4) | BIT(3)),
+ [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0,
+ BIT(5) | BIT(4) | BIT(3)),
+ [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0,
+ BIT(5) | BIT(4) | BIT(3)),
+ [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0,
+ BIT(5) | BIT(4) | BIT(3)),
+ [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),
+ [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)),
+ [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)),
+};
+
+static const struct ccu_reset_controller_data k3_apmu_reset_data = {
+ .reset_data = k3_apmu_resets,
+ .count = ARRAY_SIZE(k3_apmu_resets),
+};
+
+static const struct ccu_reset_data k3_dciu_resets[] = {
+ [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)),
+ [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)),
+ [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)),
+ [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)),
+ [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)),
+};
+
+static const struct ccu_reset_controller_data k3_dciu_reset_data = {
+ .reset_data = k3_dciu_resets,
+ .count = ARRAY_SIZE(k3_dciu_resets),
+};
+
+#define K3_AUX_DEV_ID(_unit) \
+ { \
+ .name = "spacemit_ccu.k3-" #_unit "-reset", \
+ .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \
+ }
+
+static const struct auxiliary_device_id spacemit_k3_reset_ids[] = {
+ K3_AUX_DEV_ID(mpmu),
+ K3_AUX_DEV_ID(apbc),
+ K3_AUX_DEV_ID(apmu),
+ K3_AUX_DEV_ID(dciu),
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids);
+
+static struct auxiliary_driver spacemit_k3_reset_driver = {
+ .probe = spacemit_reset_probe,
+ .id_table = spacemit_k3_reset_ids,
+};
+module_auxiliary_driver(spacemit_k3_reset_driver);
+
+MODULE_IMPORT_NS("RESET_SPACEMIT");
+MODULE_AUTHOR("Guodong Xu <guodong@riscstar.com>");
+MODULE_DESCRIPTION("SpacemiT K3 reset controller driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC
2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
` (3 preceding siblings ...)
2026-01-20 11:10 ` [PATCH v3 4/4] reset: spacemit: Add SpacemiT K3 reset driver Guodong Xu
@ 2026-01-20 12:19 ` Guodong Xu
2026-01-23 1:24 ` Yixun Lan
5 siblings, 0 replies; 7+ messages in thread
From: Guodong Xu @ 2026-01-20 12:19 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu
Cc: Alex Elder, linux-kernel, devicetree, linux-riscv, spacemit,
Krzysztof Kozlowski
On Tue, Jan 20, 2026 at 7:11 PM Guodong Xu <guodong@riscstar.com> wrote:
>
> This series adds support for the reset controller found on the SpacemiT
> K3 SoC.
>
> The clock driver changes, which defined new auxiliary device name
> patterns for reset on K1 and K3, have been applied to the clock tree.
> To facilitate merging, Yixun Lan has created an immutable tag
> (spacemit-clkrst-v6.20-3) within his pull request to the clock
> subsystem [1]. Hence, the dependencies mentioned in v2 have now
Apologies, I noticed the link [1] referenced was incorrect. Fixed below.
> been deblocked, making the reset driver ready to be applied, if it
> gets approval from review.
>
> In this version (v3), the entire series has been rebased and tested
> on top of the linux-next tag: next-20260119.
>
> General informaiton about the series:
>
> The K3 reset controller shares the same architecture as the K1. To
> facilitate support for both and future SoCs, the existing K1 reset
> driver is refactored with the following changes:
>
> 1. The existing K1 driver is moved to a dedicated 'drivers/reset/spacemit/'
> directory.
> 2. Common reset operations are extracted into reset-spacemit-common.{c,h}
>
> The K3 driver is implemented using this common infrastructure.
>
> Link: https://lore.kernel.org/linux-clk/20260114060410.3340540-1-yixun.lan@gmail.com/ [1]
Please use this link for the immutable tag reference instead:
Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1]
The code remains unchanged.
Best regards,
Guodong Xu
>
> Changes in v3:
> - Updated dependency status and base information.
> - Patch 1:
> Add Acked-by from Krzysztof and Alex.
> - Patch 2:
> Removed trailing blank line from Makefile.
> - Patch 1/2/3/4:
> Add Acked-by / Reviewed-by from Alex Elder.
>
> - Link to v2: https://lore.kernel.org/r/20260108-k3-reset-v2-0-457df235efe9@riscstar.com
>
> Changes in v2:
> - Patch 1:
> Update the commit message to explain the why.
> Update the spacemit,k1-syscon.yaml to point to k3 reset IDs
> header file.
> - Patch 3:
> Use dev->driver->owner for the reset controller owner instead of
> THIS_MODULE to fix the module reference counting issue pointed out
> by Krzysztof Kozlowski.
> - Patch 3 and 4:
> Update the K1_AUX_DEV_ID and K3_AUX_DEV_ID macros to a simpler but direct
> form, one benefit is to improve the code readability. More discussion
> can be found in Link [4].
> Link to v1: https://lore.kernel.org/r/20251229-k3-reset-v1-0-eda0747bded3@riscstar.com
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> Guodong Xu (4):
> dt-bindings: soc: spacemit: Add K3 reset support and IDs
> reset: Create subdirectory for SpacemiT drivers
> reset: spacemit: Extract common K1 reset code
> reset: spacemit: Add SpacemiT K3 reset driver
>
> .../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 8 +-
> drivers/reset/Kconfig | 12 +-
> drivers/reset/Makefile | 2 +-
> drivers/reset/spacemit/Kconfig | 36 ++++
> drivers/reset/spacemit/Makefile | 5 +
> drivers/reset/spacemit/reset-spacemit-common.c | 77 +++++++
> drivers/reset/spacemit/reset-spacemit-common.h | 42 ++++
> .../reset-spacemit-k1.c} | 107 +---------
> drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++
> include/dt-bindings/reset/spacemit,k3-resets.h | 171 +++++++++++++++
> 10 files changed, 583 insertions(+), 110 deletions(-)
> ---
> base-commit: 6ada99659c6d6a0cde83e6c0f4ed0ef0ba1867e1
> change-id: 20251229-k3-reset-8d9b751ef391
>
> Best regards,
> --
> Guodong Xu <guodong@riscstar.com>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC
2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
` (4 preceding siblings ...)
2026-01-20 12:19 ` [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
@ 2026-01-23 1:24 ` Yixun Lan
5 siblings, 0 replies; 7+ messages in thread
From: Yixun Lan @ 2026-01-23 1:24 UTC (permalink / raw)
To: Guodong Xu
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Haylen Chu, Alex Elder, linux-kernel, devicetree,
linux-riscv, spacemit, Krzysztof Kozlowski
Hi Philipp Zabel,
On 19:10 Tue 20 Jan , Guodong Xu wrote:
> This series adds support for the reset controller found on the SpacemiT
> K3 SoC.
>
> The clock driver changes, which defined new auxiliary device name
> patterns for reset on K1 and K3, have been applied to the clock tree.
> To facilitate merging, Yixun Lan has created an immutable tag
> (spacemit-clkrst-v6.20-3) within his pull request to the clock
> subsystem [1]. Hence, the dependencies mentioned in v2 have now
> been deblocked, making the reset driver ready to be applied, if it
> gets approval from review.
>
> In this version (v3), the entire series has been rebased and tested
> on top of the linux-next tag: next-20260119.
>
> General informaiton about the series:
>
> The K3 reset controller shares the same architecture as the K1. To
> facilitate support for both and future SoCs, the existing K1 reset
> driver is refactored with the following changes:
>
> 1. The existing K1 driver is moved to a dedicated 'drivers/reset/spacemit/'
> directory.
> 2. Common reset operations are extracted into reset-spacemit-common.{c,h}
>
> The K3 driver is implemented using this common infrastructure.
>
> Link: https://lore.kernel.org/linux-clk/20260114060410.3340540-1-yixun.lan@gmail.com/ [1]
>
Just want to ping this with my SpacemiT maintainer position, the reset
driver is the last piece that I hope can be accepted during this merge
window (target the v6.20 release), it would help other drivers since it
is a fundamental dependency..
The clock PR which is a dependency for reset has been pulled by Stephen[2],
and the driver also has been tested for a while locally
https://lore.kernel.org/r/176902257445.4027.5972559722832621691@lazor [2]
Reviewed-by: Yixun Lan <dlan@kernel.org>
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-01-23 1:24 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2026-01-20 11:10 [PATCH v3 0/4] reset: spacemit: Add support for SpacemiT K3 SoC Guodong Xu
2026-01-20 11:10 ` [PATCH v3 1/4] dt-bindings: soc: spacemit: Add K3 reset support and IDs Guodong Xu
2026-01-20 11:10 ` [PATCH v3 2/4] reset: Create subdirectory for SpacemiT drivers Guodong Xu
2026-01-20 11:10 ` [PATCH v3 3/4] reset: spacemit: Extract common K1 reset code Guodong Xu
2026-01-20 11:10 ` [PATCH v3 4/4] reset: spacemit: Add SpacemiT K3 reset driver Guodong Xu
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