Re: [PATCH v2 2/3] gpio: tegra186: Add support for Tegra264

Jon Hunter
2026-01-23T09:29:02Z

On 23/01/2026 06:41, Prathamesh Shete wrote:
> Extend the existing Tegra186 GPIO controller driver with support for the
> GPIO controller found on Tegra264.
>
> Use the "wakeup-parent" phandle from the GPIO device tree node to
> ensure the GPIO driver associates with the intended PMC device.
> Relying only on compatible-based lookup can select an unexpected
> PMC node, so fall back to compatible-based lookup when the phandle
> is not present.
>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
> Changes in v2:
> * Use “wakeup-parent” instead of "nvidia,pmc" and include the renamed header.
> ---
> drivers/gpio/gpio-tegra186.c | 90 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
> index b1498b59a921..9c874f07be75 100644
> --- a/drivers/gpio/gpio-tegra186.c
> +++ b/drivers/gpio/gpio-tegra186.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2016-2025 NVIDIA Corporation
> + * Copyright (c) 2016-2026 NVIDIA Corporation
> *
> * Author: Thierry Reding <treding@nvidia.com>
> * Dipen Patel <dpatel@nvidia.com>
> @@ -21,6 +21,7 @@
> #include <dt-bindings/gpio/tegra234-gpio.h>
> #include <dt-bindings/gpio/tegra241-gpio.h>
> #include <dt-bindings/gpio/tegra256-gpio.h>
> +#include <dt-bindings/gpio/nvidia,tegra264-gpio.h>
>
> /* security registers */
> #define TEGRA186_GPIO_CTL_SCR 0x0c
> @@ -1001,7 +1002,9 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
> if (gpio->soc->num_irqs_per_bank > 1)
> tegra186_gpio_init_route_mapping(gpio);
>
> - np = of_find_matching_node(NULL, tegra186_pmc_of_match);
> + np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0);
> + if (!np)
> + np = of_find_matching_node(NULL, tegra186_pmc_of_match);
> if (np) {
> if (of_device_is_available(np)) {
> irq->parent_domain = irq_find_host(np);
> @@ -1277,6 +1280,80 @@ static const struct tegra_gpio_soc tegra241_aon_soc = {
> .has_vm_support = false,
> };
>
> +#define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
> + TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins)
> +
> +static const struct tegra_gpio_port tegra264_main_ports[] = {
> + TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8),
> + TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5),
> + TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8),
> + TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8),
> + TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8),
> + TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8),
> + TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6),
> + TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8),
> + TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8),
> + TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8),
> + TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2),
> + TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7),
> + TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8),
> + TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8),
> + TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8),
> + TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6),
> + TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8),
> + TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8),
> + TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3),
> +};
> +
> +static const struct tegra_gpio_soc tegra264_main_soc = {
> + .num_ports = ARRAY_SIZE(tegra264_main_ports),
> + .ports = tegra264_main_ports,
> + .name = "tegra264-gpio",
> + .instance = 0,
> + .num_irqs_per_bank = 8,
> + .has_vm_support = true,
> +};
> +
> +#define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \
> + TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins)
> +
> +static const struct tegra_gpio_port tegra264_aon_ports[] = {
> + TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8),
> + TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2),
> + TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8),
> + TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8),
> + TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4)
> +};
> +
> +static const struct tegra_gpio_soc tegra264_aon_soc = {
> + .num_ports = ARRAY_SIZE(tegra264_aon_ports),
> + .ports = tegra264_aon_ports,
> + .name = "tegra264-gpio-aon",
> + .instance = 1,
> + .num_irqs_per_bank = 8,
> + .has_vm_support = true,
> +};
> +
> +#define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \
> + TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins)
> +
> +static const struct tegra_gpio_port tegra264_uphy_ports[] = {
> + TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6),
> + TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8),
> + TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3),
> + TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8),
> + TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4),
> +};
> +
> +static const struct tegra_gpio_soc tegra264_uphy_soc = {
> + .num_ports = ARRAY_SIZE(tegra264_uphy_ports),
> + .ports = tegra264_uphy_ports,
> + .name = "tegra264-gpio-uphy",
> + .instance = 2,
> + .num_irqs_per_bank = 8,
> + .has_vm_support = true,
> +};
> +
> #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
> TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins)
>
> @@ -1368,6 +1445,15 @@ static const struct of_device_id tegra186_gpio_of_match[] = {
> }, {
> .compatible = "nvidia,tegra256-gpio",
> .data = &tegra256_main_soc
> + }, {
> + .compatible = "nvidia,tegra264-gpio",
> + .data = &tegra264_main_soc
> + }, {
> + .compatible = "nvidia,tegra264-gpio-aon",
> + .data = &tegra264_aon_soc
> + }, {
> + .compatible = "nvidia,tegra264-gpio-uphy",
> + .data = &tegra264_uphy_soc
> }, {
> /* sentinel */
> }

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Thanks!
Jon
--
nvpublic