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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF00004FBE.mail.protection.outlook.com (10.167.243.184) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Mon, 26 Jan 2026 22:42:20 +0000 Received: from gaul.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 26 Jan 2026 16:42:18 -0600 From: Kim Phillips To: , , , CC: Sean Christopherson , Paolo Bonzini , K Prateek Nayak , "Nikunj A Dadhania" , Tom Lendacky , "Michael Roth" , Borislav Petkov , Borislav Petkov , Naveen Rao , David Kaplan , Kim Phillips Subject: [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry Date: Mon, 26 Jan 2026 16:42:03 -0600 Message-ID: <20260126224205.1442196-1-kim.phillips@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBE:EE_|IA1PR12MB6067:EE_ X-MS-Office365-Filtering-Correlation-Id: b6b1d79f-6a8e-435d-0fc9-08de5d2c2a76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 22:42:20.5090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6b1d79f-6a8e-435d-0fc9-08de5d2c2a76 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6067 AMD EPYC 5th generation and above processors support IBPB-on-Entry for SNP guests. By invoking an Indirect Branch Prediction Barrier (IBPB) on VMRUN, old indirect branch predictions are prevented from influencing indirect branches within the guest. The first patch is guest-side support which unmasks the Zen5+ feature bit to allow kernel guests to set the feature. The second patch is host-side support that checks the CPUID and then sets the feature bit in the VMSA supported features mask. Based on https://github.com/kvm-x86/linux kvm-x86/next (kvm-x86-next-2026.01.23, e81f7c908e16). This series also available here: https://github.com/AMDESE/linux/tree/ibpb-on-entry-latest Advance qemu bits (to add ibpb-on-entry=on/off switch) available here: https://github.com/AMDESE/qemu/tree/ibpb-on-entry-latest Qemu bits will be posted upstream once kernel bits are merged. They depend on Naveen Rao's "target/i386: SEV: Add support for enabling VMSA SEV features": https://lore.kernel.org/qemu-devel/cover.1761648149.git.naveen@kernel.org/ Kim Phillips (2): KVM: SEV: IBPB-on-Entry guest support KVM: SEV: Add support for IBPB-on-Entry arch/x86/boot/compressed/sev.c | 1 + arch/x86/coco/sev/core.c | 1 + arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 5 ++++- arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/sev.c | 9 ++++++++- 6 files changed, 16 insertions(+), 2 deletions(-) base-commit: e81f7c908e1664233974b9f20beead78cde6343a -- 2.43.0