From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6140342507; Tue, 27 Jan 2026 10:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769510412; cv=none; b=gN4sSIBVXN3afD2ye0TUPHZDL/BgmtcWb9W58n83LRZxZSqVeTICmBUTJS4C7YoaKfB24ZFpB+yqjpBufxSfaazYF5ziuD6nFxiyGYGCFFecy2+LkKLsXu0idtEfhGfxpgpU5EIE3Pm5rYfezfBBfSpkJciHHkeIMFa75cQJwWw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769510412; c=relaxed/simple; bh=RhMDW66jJzShSPyLcxa+n/Druwp8ki9Nu3SCAZoABSo=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=irR0ZMZXD1JksEf6Ck5owHHNLpT+4y0ERpkGVaQjUrxCDWFbBHutsuFz9nkQkLjEPJYUU1PY7TXpWj3EoimRiFrmdP6+/HFBE6mmQHTieVvICIRZYuRMhm/UQYC//TYYS/jWRbZDocNHR1v11AoQEqvVcglOQ63e773wk32xg3Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.224.83]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4f0hjb5JWNzJ46BB; Tue, 27 Jan 2026 18:39:31 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 7F1AA40569; Tue, 27 Jan 2026 18:40:07 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 27 Jan 2026 10:39:32 +0000 Date: Tue, 27 Jan 2026 10:39:31 +0000 From: Jonathan Cameron To: Shuai Xue CC: , , , , , , , , , , Subject: Re: [PATCH v7 4/5] PCI/AER: Clear both AER fatal and non-fatal status Message-ID: <20260127103931.000058bb@huawei.com> In-Reply-To: <20260124074557.73961-5-xueshuai@linux.alibaba.com> References: <20260124074557.73961-1-xueshuai@linux.alibaba.com> <20260124074557.73961-5-xueshuai@linux.alibaba.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500012.china.huawei.com (7.191.174.4) To dubpeml500005.china.huawei.com (7.214.145.207) On Sat, 24 Jan 2026 15:45:56 +0800 Shuai Xue wrote: > The DPC driver clears AER fatal status for the port that reported the > error, but not for the downstream device that deteced the error. The > current recovery code only clears non-fatal AER status, leaving fatal > status bits set in the error device. > > Use pci_aer_raw_clear_status() to clear both fatal and non-fatal error > status in the error device, ensuring all AER status bits are properly > cleared after recovery. > > Fixes: aa344bc8b727 ("PCI/ERR: Clear AER status only when we control AER") > Cc: stable@vger.kernel.org > Signed-off-by: Shuai Xue Shouldn't this be first patch in series to make it easier to backport? Otherwise seems reasonable to me, but others know these flows better than me so hopefully we'll get some more review. Reviewed-by: Jonathan Cameron > --- > drivers/pci/pcie/err.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c > index 0780ea09478b..5e463efc3d05 100644 > --- a/drivers/pci/pcie/err.c > +++ b/drivers/pci/pcie/err.c > @@ -285,7 +285,7 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, > */ > if (host->native_aer || pcie_ports_native) { > pcie_clear_device_status(dev); > - pci_aer_clear_nonfatal_status(dev); > + pci_aer_raw_clear_status(dev); > } > > pci_walk_bridge(bridge, pci_pm_runtime_put, NULL);