[PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Icenowy Zheng]

This patchset tries to add support for Loongson 7A1000 PCH's LPC IRQ
controller to MIPS-based Loongson systems.

LPC, from software's perspective of view, is just ISA, so the IRQs
should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
machines handled it, the setup is fragile and depends on its specific
setup sequence (allocating the LPC IRQs first, and then allocate the
parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
breaks this fragile sequence, so the first commit is created to address
for this issue (by reserving ISA IRQs from the dynamic IRQ allocation
space).

Then the remaining commits are just adding OF(DT) based initialization
of PCH LPC IRQ controller, like what happened on PCH PIC.

Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
integrated ones. I don't own a LoongArch-based device with LPC
peripherals, so test on LoongArch machines are welcomed.

Icenowy Zheng (8):
  genirq: reserve NR_IRQS_LEGACY IRQs by default
  dt-bindings: interrupt-controller: add LS7A PCH LPC
  irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init
  irqchip/loongson-pch-lpc: guard ACPI init code with CONFIG_ACPI
  irqchip/loongson-pch-lpc: add OF init code
  irqchip/loongson-pch-lpc: enable building on MIPS Loongson64
  MIPS: Loongson64: dts: sort nodes
  MIPS: Loongson64: dts: add node for LS7A PCH LPC

 .../loongson,pch-lpc.yaml                     | 52 +++++++++++
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi     | 17 +++-
 drivers/irqchip/Kconfig                       |  1 -
 drivers/irqchip/irq-loongson-pch-lpc.c        | 86 ++++++++++++++-----
 kernel/softirq.c                              |  2 +-
 5 files changed, 132 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

-- 
2.52.0

[PATCH 1/8] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by default

[Icenowy Zheng]

Several architectures define NR_IRQS_LEGACY to reserve a low range of IRQ
numbers for fixed legacy allocations (e.g. ISA interrupts) which should
not be handed out by the dynamic IRQ allocator.

arch_dynirq_lower_bound() exists to enforce this, but today only x86 wires
it up. In the current boot order this typically works because legacy IRQ
domains register early and claim the low IRQ numbers first; however, that
assumption breaks if the legacy controller is probed later.

Make the default arch_dynirq_lower_bound() implementation honour
NR_IRQS_LEGACY by clamping the allocation start to at least that value.

Architectures that do not define NR_IRQS_LEGACY keep the current behaviour
(effectively 0). Arm/PowerPC/MIPS/LoongArch use legacy IRQ domains for ISA
interrupts and benefit from this change. x86 and s390 already provide their
own implementations.

Cc: linux-s390@vger.kernel.org
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Cc: Alexander Gordeev <agordeev@linux.ibm.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
If this change turns out to be problematic for any architecture, we can
always override arch_dynirq_lower_bound() for MIPS and LoongArch only.

BTW it looks that S390 has a arch_dynirq_lower_bound() override that has
the same behavior, but not with the same code. This is why S390
maintainers are Cc'ed by this patch.

 kernel/softirq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/softirq.c b/kernel/softirq.c
index 77198911b8dd4..cdc77d52c36b2 100644
--- a/kernel/softirq.c
+++ b/kernel/softirq.c
@@ -1184,5 +1184,5 @@ int __init __weak arch_early_irq_init(void)
 
 unsigned int __weak arch_dynirq_lower_bound(unsigned int from)
 {
-	return from;
+	return MAX(from, NR_IRQS_LEGACY);
 }
-- 
2.52.0

[PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Icenowy Zheng]

Loongson 7A series PCH contains an LPC controller with an interrupt
controller.

Add the device tree binding for the interrupt controller.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
new file mode 100644
index 0000000000000..c00fbf31f47f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCH LPC Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description:
+  This interrupt controller is found in the Loongson LS7A family of PCH for
+  accepting interrupts sent by LPC-connected peripherals and signalling PIC
+  via a single interrupt line when interrupts are available.
+
+properties:
+  compatible:
+    const: loongson,pch-lpc-1.0
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  '#interrupt-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - interrupts
+  - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    lpc: interrupt-controller@10002000 {
+      compatible = "loongson,pch-lpc-1.0";
+      reg = <0x10002000 0x400>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      interrupt-parent = <&pic>;
+      interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...
-- 
2.52.0

Re: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Rob Herring]

On Sat, Jan 31, 2026 at 05:45:41PM +0800, Icenowy Zheng wrote:
> Loongson 7A series PCH contains an LPC controller with an interrupt
> controller.
> 
> Add the device tree binding for the interrupt controller.
> 
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
>  .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> new file mode 100644
> index 0000000000000..c00fbf31f47f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson PCH LPC Controller
> +
> +maintainers:
> +  - Jiaxun Yang <jiaxun.yang@flygoat.com>
> +
> +description:
> +  This interrupt controller is found in the Loongson LS7A family of PCH for
> +  accepting interrupts sent by LPC-connected peripherals and signalling PIC
> +  via a single interrupt line when interrupts are available.
> +
> +properties:
> +  compatible:
> +    const: loongson,pch-lpc-1.0

Where does 1.0 come from? We don't do version numbers generally unless 
you define where the versions come from (e.g. Soft IP releases for 
FPGAs). I would have expected "ls7a" in the compatible instead.

Rob

Re: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Icenowy Zheng]

在 2026-02-09星期一的 17:48 -0600，Rob Herring写道：
> On Sat, Jan 31, 2026 at 05:45:41PM +0800, Icenowy Zheng wrote:
> > Loongson 7A series PCH contains an LPC controller with an interrupt
> > controller.
> > 
> > Add the device tree binding for the interrupt controller.
> > 
> > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> > ---
> >  .../loongson,pch-lpc.yaml                     | 52
> > +++++++++++++++++++
> >  1 file changed, 52 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > b/Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > new file mode 100644
> > index 0000000000000..c00fbf31f47f0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Loongson PCH LPC Controller
> > +
> > +maintainers:
> > +  - Jiaxun Yang <jiaxun.yang@flygoat.com>
> > +
> > +description:
> > +  This interrupt controller is found in the Loongson LS7A family
> > of PCH for
> > +  accepting interrupts sent by LPC-connected peripherals and
> > signalling PIC
> > +  via a single interrupt line when interrupts are available.
> > +
> > +properties:
> > +  compatible:
> > +    const: loongson,pch-lpc-1.0
> 
> Where does 1.0 come from? We don't do version numbers generally
> unless 
> you define where the versions come from (e.g. Soft IP releases for 
> FPGAs). I would have expected "ls7a" in the compatible instead.

Well this replicates what's set on PCH PIC, although I am okay to
change it to `7a1000-pch-lpc` .
Thanks
Icenowy

> 
> Rob
> 

Re: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Icenowy Zheng]

在 2026-02-09星期一的 17:48 -0600，Rob Herring写道：
> On Sat, Jan 31, 2026 at 05:45:41PM +0800, Icenowy Zheng wrote:
> > Loongson 7A series PCH contains an LPC controller with an interrupt
> > controller.
> > 
> > Add the device tree binding for the interrupt controller.
> > 
> > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> > ---
> >  .../loongson,pch-lpc.yaml                     | 52
> > +++++++++++++++++++
> >  1 file changed, 52 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > b/Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > new file mode 100644
> > index 0000000000000..c00fbf31f47f0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-
> > controller/loongson,pch-lpc.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Loongson PCH LPC Controller
> > +
> > +maintainers:
> > +  - Jiaxun Yang <jiaxun.yang@flygoat.com>
> > +
> > +description:
> > +  This interrupt controller is found in the Loongson LS7A family
> > of PCH for
> > +  accepting interrupts sent by LPC-connected peripherals and
> > signalling PIC
> > +  via a single interrupt line when interrupts are available.
> > +
> > +properties:
> > +  compatible:
> > +    const: loongson,pch-lpc-1.0
> 
> Where does 1.0 come from? We don't do version numbers generally
> unless 
> you define where the versions come from (e.g. Soft IP releases for 
> FPGAs). I would have expected "ls7a" in the compatible instead.

I originally followed the behavior of PCH PIC; however after asking
Jiaxun offlist, I was noticed about a register on the 7A1000 user
manual in the PIC that identifies the PIC version number; such version
number register does not exist for LPC part.

I will switch to ls7a-lpc or ls7a1000-lpc. Newer compatible strings in
the 2K series (LoongArch ones) come with the whole model number, I
don't know whether this is needed for 7A1000 (although it looks like
that 7A2000 has the same 
> 
> Rob
> 

Re: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Huacai Chen]

On Tue, Feb 10, 2026 at 6:51 PM Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>
> 在 2026-02-09星期一的 17:48 -0600，Rob Herring写道：
> > On Sat, Jan 31, 2026 at 05:45:41PM +0800, Icenowy Zheng wrote:
> > > Loongson 7A series PCH contains an LPC controller with an interrupt
> > > controller.
> > >
> > > Add the device tree binding for the interrupt controller.
> > >
> > > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> > > ---
> > >  .../loongson,pch-lpc.yaml                     | 52
> > > +++++++++++++++++++
> > >  1 file changed, 52 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> > > controller/loongson,pch-lpc.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-
> > > controller/loongson,pch-lpc.yaml
> > > b/Documentation/devicetree/bindings/interrupt-
> > > controller/loongson,pch-lpc.yaml
> > > new file mode 100644
> > > index 0000000000000..c00fbf31f47f0
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/interrupt-
> > > controller/loongson,pch-lpc.yaml
> > > @@ -0,0 +1,52 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Loongson PCH LPC Controller
> > > +
> > > +maintainers:
> > > +  - Jiaxun Yang <jiaxun.yang@flygoat.com>
> > > +
> > > +description:
> > > +  This interrupt controller is found in the Loongson LS7A family
> > > of PCH for
> > > +  accepting interrupts sent by LPC-connected peripherals and
> > > signalling PIC
> > > +  via a single interrupt line when interrupts are available.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: loongson,pch-lpc-1.0
> >
> > Where does 1.0 come from? We don't do version numbers generally
> > unless
> > you define where the versions come from (e.g. Soft IP releases for
> > FPGAs). I would have expected "ls7a" in the compatible instead.
>
> I originally followed the behavior of PCH PIC; however after asking
> Jiaxun offlist, I was noticed about a register on the 7A1000 user
> manual in the PIC that identifies the PIC version number; such version
> number register does not exist for LPC part.
>
> I will switch to ls7a-lpc or ls7a1000-lpc. Newer compatible strings in
> the 2K series (LoongArch ones) come with the whole model number, I
> don't know whether this is needed for 7A1000 (although it looks like
> that 7A2000 has the same
Yes, they are the same, so I think ls7a-lpc is just OK.

Huacai

> >
> > Rob
> >
>

[PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init

[Icenowy Zheng]

A lot of code could be shared between the current ACPI init flow with
the possible OF init flow.

Extract them to a dedicated function.

The re-ordering of parent IRQ acquisition requires the arch code to
reserve legacy IRQs from dynirq allocation via
overriding arch_dynirq_lower_bound(), otherwise the parent of LPC
irqchip will be allocated to the intended static range of LPC IRQs,
which leads to allocation failure of LPC IRQs.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 56 +++++++++++++++++---------
 1 file changed, 36 insertions(+), 20 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 3a125f3e42873..4507000b991a6 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -175,13 +175,11 @@ static struct syscore pch_lpc_syscore = {
 	.ops = &pch_lpc_syscore_ops,
 };
 
-int __init pch_lpc_acpi_init(struct irq_domain *parent,
-					struct acpi_madt_lpc_pic *acpi_pchlpc)
+static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
+				struct fwnode_handle *irq_handle,
+				int parent_irq)
 {
-	int parent_irq;
 	struct pch_lpc *priv;
-	struct irq_fwspec fwspec;
-	struct fwnode_handle *irq_handle;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -189,7 +187,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	raw_spin_lock_init(&priv->lpc_lock);
 
-	priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
+	priv->base = ioremap(addr, size);
 	if (!priv->base)
 		goto free_priv;
 
@@ -198,12 +196,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 		goto iounmap_base;
 	}
 
-	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
-	if (!irq_handle) {
-		pr_err("Unable to allocate domain handle\n");
-		goto iounmap_base;
-	}
-
 	/*
 	 * The LPC interrupt controller is a legacy i8259-compatible device,
 	 * which requires a static 1:1 mapping for IRQs 0-15.
@@ -213,15 +205,10 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 						    &pch_lpc_domain_ops, priv);
 	if (!priv->lpc_domain) {
 		pr_err("Failed to create IRQ domain\n");
-		goto free_irq_handle;
+		goto iounmap_base;
 	}
 	pch_lpc_reset(priv);
 
-	fwspec.fwnode = parent->fwnode;
-	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
-	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
-	fwspec.param_count = 2;
-	parent_irq = irq_create_fwspec_mapping(&fwspec);
 	irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
 
 	pch_lpc_priv = priv;
@@ -230,8 +217,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return 0;
 
-free_irq_handle:
-	irq_domain_free_fwnode(irq_handle);
 iounmap_base:
 	iounmap(priv->base);
 free_priv:
@@ -239,3 +224,34 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return -ENOMEM;
 }
+
+int __init pch_lpc_acpi_init(struct irq_domain *parent,
+					struct acpi_madt_lpc_pic *acpi_pchlpc)
+{
+	int parent_irq;
+	struct pch_lpc *priv;
+	struct irq_fwspec fwspec;
+	struct fwnode_handle *irq_handle;
+	int ret;
+
+	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
+	if (!irq_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		return -ENOMEM;
+	}
+
+	fwspec.fwnode = parent->fwnode;
+	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
+	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+	fwspec.param_count = 2;
+	parent_irq = irq_create_fwspec_mapping(&fwspec);
+
+	ret = pch_lpc_init(acpi_pchlpc->address, acpi_pchlpc->size,
+			   irq_handle, parent_irq);
+	if (ret) {
+		irq_domain_free_fwnode(irq_handle);
+		return ret;
+	}
+
+	return 0;
+}
-- 
2.52.0

Re: [PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init

[kernel test robot]

Hi Icenowy,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tip/irq/core]
[also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.19-rc7 next-20260130]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Icenowy-Zheng/genirq-reserve-NR_IRQS_LEGACY-IRQs-in-dynirq-by-default/20260131-175403
base:   tip/irq/core
patch link:    https://lore.kernel.org/r/20260131094547.455916-4-zhengxingda%40iscas.ac.cn
patch subject: [PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init
config: loongarch-allnoconfig (https://download.01.org/0day-ci/archive/20260131/202601312251.S1bOvHGe-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260131/202601312251.S1bOvHGe-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601312251.S1bOvHGe-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/irqchip/irq-loongson-pch-lpc.c:232:18: warning: unused variable 'priv' [-Wunused-variable]
     232 |         struct pch_lpc *priv;
         |                         ^~~~
   1 warning generated.


vim +/priv +232 drivers/irqchip/irq-loongson-pch-lpc.c

   227	
   228	int __init pch_lpc_acpi_init(struct irq_domain *parent,
   229						struct acpi_madt_lpc_pic *acpi_pchlpc)
   230	{
   231		int parent_irq;
 > 232		struct pch_lpc *priv;

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init

[Thomas Gleixner]

On Sat, Jan 31 2026 at 17:45, Icenowy Zheng wrote:
> A lot of code could be shared between the current ACPI init flow with

s/could/can/

> the possible OF init flow.
>
> Extract them to a dedicated function.

Extract it ..

> The re-ordering of parent IRQ acquisition requires the arch code to

of the parent interrupt acquisition ... the architecture code ...

> reserve legacy IRQs from dynirq allocation via

... legacy interrupts from the dynamic allocation by overriding

> overriding arch_dynirq_lower_bound(), otherwise the parent of LPC

of the LPC ... allocated at the ...

> irqchip will be allocated to the intended static range of LPC IRQs,

LPC interrupts

> which leads to allocation failure of LPC IRQs.

LPC interrupts

Please use proper sentences and words. This is not an acronym competition.

> +static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
> +				struct fwnode_handle *irq_handle,
> +				int parent_irq)

Avoid extensive line breaks. You have 100 characters

> +int __init pch_lpc_acpi_init(struct irq_domain *parent,
> +					struct acpi_madt_lpc_pic *acpi_pchlpc)

Either avoid the line break or align the second line argument with the
first argument. 

> +{
> +	int parent_irq;
> +	struct pch_lpc *priv;
> +	struct irq_fwspec fwspec;
> +	struct fwnode_handle *irq_handle;
> +	int ret;

 https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations

Thanks,

        tglx

[PATCH 4/8] irqchip/loongson-pch-lpc: guard ACPI init code with CONFIG_ACPI

[Icenowy Zheng]

As OF-based initialization is going to be added to the driver, guard the
ACPI-based initialization code with CONFIG_ACPI.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 4507000b991a6..96489e031d34e 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -225,6 +225,7 @@ static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
 	return -ENOMEM;
 }
 
+#ifdef CONFIG_ACPI
 int __init pch_lpc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lpc_pic *acpi_pchlpc)
 {
@@ -255,3 +256,4 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return 0;
 }
+#endif /* CONFIG_ACPI */
-- 
2.52.0

[PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[Icenowy Zheng]

As the (kernel-internally) OF-based MIPS Loongson-3 systems can also
have PCH LPC interrupt controller, add OF-based initialization code for
the driver.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 28 ++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 96489e031d34e..0baa93028abf4 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -13,6 +13,8 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/syscore_ops.h>
 
 #include "irq-loongson.h"
@@ -257,3 +259,29 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 	return 0;
 }
 #endif /* CONFIG_ACPI */
+
+#ifdef CONFIG_OF
+static int pch_lpc_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	int parent_irq;
+	struct fwnode_handle *irq_handle;
+	struct resource res;
+
+	if (of_address_to_resource(node, 0, &res))
+		return -EINVAL;
+
+	parent_irq = irq_of_parse_and_map(node, 0);
+	if (!parent_irq) {
+		pr_err("Failed to get the parent IRQ for LPC IRQs\n");
+		return -EINVAL;
+	}
+
+	irq_handle = of_fwnode_handle(node);
+
+	return pch_lpc_init(res.start, resource_size(&res), irq_handle,
+			    parent_irq);
+}
+
+IRQCHIP_DECLARE(pch_lpc, "loongson,pch-lpc-1.0", pch_lpc_of_init);
+#endif /* CONFIG_OF */
-- 
2.52.0

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[kernel test robot]

Hi Icenowy,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tip/irq/core]
[also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.19-rc7 next-20260130]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Icenowy-Zheng/genirq-reserve-NR_IRQS_LEGACY-IRQs-in-dynirq-by-default/20260131-175403
base:   tip/irq/core
patch link:    https://lore.kernel.org/r/20260131094547.455916-6-zhengxingda%40iscas.ac.cn
patch subject: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code
config: loongarch-allnoconfig (https://download.01.org/0day-ci/archive/20260201/202602010337.D6tyoDtw-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260201/202602010337.D6tyoDtw-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602010337.D6tyoDtw-lkp@intel.com/

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> WARNING: modpost: vmlinux: section mismatch in reference: pch_lpc_of_init+0xa8 (section: .text) -> pch_lpc_init (section: .init.text)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[Huacai Chen]

Hi, Icenowy,

On Sat, Jan 31, 2026 at 5:46 PM Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>
> As the (kernel-internally) OF-based MIPS Loongson-3 systems can also
> have PCH LPC interrupt controller, add OF-based initialization code for
> the driver.
I think Patch-3/4/5 can be combined to a single one.

Huacai
>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
>  drivers/irqchip/irq-loongson-pch-lpc.c | 28 ++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
> index 96489e031d34e..0baa93028abf4 100644
> --- a/drivers/irqchip/irq-loongson-pch-lpc.c
> +++ b/drivers/irqchip/irq-loongson-pch-lpc.c
> @@ -13,6 +13,8 @@
>  #include <linux/irqchip/chained_irq.h>
>  #include <linux/irqdomain.h>
>  #include <linux/kernel.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
>  #include <linux/syscore_ops.h>
>
>  #include "irq-loongson.h"
> @@ -257,3 +259,29 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
>         return 0;
>  }
>  #endif /* CONFIG_ACPI */
> +
> +#ifdef CONFIG_OF
> +static int pch_lpc_of_init(struct device_node *node,
> +                               struct device_node *parent)
> +{
> +       int parent_irq;
> +       struct fwnode_handle *irq_handle;
> +       struct resource res;
> +
> +       if (of_address_to_resource(node, 0, &res))
> +               return -EINVAL;
> +
> +       parent_irq = irq_of_parse_and_map(node, 0);
> +       if (!parent_irq) {
> +               pr_err("Failed to get the parent IRQ for LPC IRQs\n");
> +               return -EINVAL;
> +       }
> +
> +       irq_handle = of_fwnode_handle(node);
> +
> +       return pch_lpc_init(res.start, resource_size(&res), irq_handle,
> +                           parent_irq);
> +}
> +
> +IRQCHIP_DECLARE(pch_lpc, "loongson,pch-lpc-1.0", pch_lpc_of_init);
> +#endif /* CONFIG_OF */
> --
> 2.52.0
>

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[Thomas Gleixner]

On Sun, Feb 01 2026 at 10:33, Huacai Chen wrote:
> Hi, Icenowy,
>
> On Sat, Jan 31, 2026 at 5:46 PM Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>>
>> As the (kernel-internally) OF-based MIPS Loongson-3 systems can also
>> have PCH LPC interrupt controller, add OF-based initialization code for
>> the driver.
> I think Patch-3/4/5 can be combined to a single one.

No. #3 should be separate, but #4/#5 combined. It's easier to review the code
rework and the new code separately.

Thanks,

        tglx

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[Thomas Gleixner]

On Sat, Jan 31 2026 at 17:45, Icenowy Zheng wrote:

> As the (kernel-internally) OF-based MIPS Loongson-3 systems can also

What are kernel-internally systems?

> have PCH LPC interrupt controller, add OF-based initialization code for

have a ... controller.

Add OF ....

> +#ifdef CONFIG_OF
> +static int pch_lpc_of_init(struct device_node *node,
> +				struct device_node *parent)

No line break required.

> +{
> +	int parent_irq;
> +	struct fwnode_handle *irq_handle;
> +	struct resource res;

Variable ordering.

> +	if (of_address_to_resource(node, 0, &res))
> +		return -EINVAL;
> +
> +	parent_irq = irq_of_parse_and_map(node, 0);
> +	if (!parent_irq) {
> +		pr_err("Failed to get the parent IRQ for LPC IRQs\n");
> +		return -EINVAL;
> +	}
> +
> +	irq_handle = of_fwnode_handle(node);
> +
> +	return pch_lpc_init(res.start, resource_size(&res), irq_handle,
> +			    parent_irq);

If pch_lpc_init() fails the parent interrupt mapping is leaked, no?

Thanks,

        tglx

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[Icenowy Zheng]

在 2026-02-01星期日的 17:19 +0100，Thomas Gleixner写道：
> On Sat, Jan 31 2026 at 17:45, Icenowy Zheng wrote:
> 
> > As the (kernel-internally) OF-based MIPS Loongson-3 systems can
> > also
> 
> What are kernel-internally systems?

I mean kernel-internally-OF-based. These devices' firmware does not
ship DT, but Linux kernel ships some DTs and pick one by arch code.

Do you have any suggestions for rewording to make this more clear? Or
should I just stop to mention this implementaion detail?

> 
> > have PCH LPC interrupt controller, add OF-based initialization code
> > for
> 
> have a ... controller.
> 
> Add OF ....
> 
> > +#ifdef CONFIG_OF
> > +static int pch_lpc_of_init(struct device_node *node,
> > +                               struct device_node *parent)
> 
> No line break required.
> 
> > +{
> > +       int parent_irq;
> > +       struct fwnode_handle *irq_handle;
> > +       struct resource res;
> 
> Variable ordering.

Is there any rule for the ordering?

> 
> > +       if (of_address_to_resource(node, 0, &res))
> > +               return -EINVAL;
> > +
> > +       parent_irq = irq_of_parse_and_map(node, 0);
> > +       if (!parent_irq) {
> > +               pr_err("Failed to get the parent IRQ for LPC
> > IRQs\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       irq_handle = of_fwnode_handle(node);
> > +
> > +       return pch_lpc_init(res.start, resource_size(&res),
> > irq_handle,
> > +                           parent_irq);
> 
> If pch_lpc_init() fails the parent interrupt mapping is leaked, no?

I don't know any reverse operation for irq_of_parse_and_map(), and most
implementations I see has no cleanup codepath for this parent IRQ.

Thanks,
Icenowy

> 
> Thanks,
> 
>         tglx

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[Thomas Gleixner]

On Mon, Feb 02 2026 at 13:50, Icenowy Zheng wrote:
> 在 2026-02-01星期日的 17:19 +0100，Thomas Gleixner写道：
>> On Sat, Jan 31 2026 at 17:45, Icenowy Zheng wrote:
>> 
>> > As the (kernel-internally) OF-based MIPS Loongson-3 systems can
>> > also
>> 
>> What are kernel-internally systems?
>
> I mean kernel-internally-OF-based. These devices' firmware does not
> ship DT, but Linux kernel ships some DTs and pick one by arch code.
>
> Do you have any suggestions for rewording to make this more clear? Or
> should I just stop to mention this implementaion detail?

It's irrelevant for the driver where the device tree comes from, no?

>> > +{
>> > +       int parent_irq;
>> > +       struct fwnode_handle *irq_handle;
>> > +       struct resource res;
>> 
>> Variable ordering.
>
> Is there any rule for the ordering?

I gave you the link in the other reply.

>> If pch_lpc_init() fails the parent interrupt mapping is leaked, no?
>
> I don't know any reverse operation for irq_of_parse_and_map(), and most

irq_dispose_mapping()

> implementations I see has no cleanup codepath for this parent IRQ.

You looked at the wrong drivers then :)

Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code

[kernel test robot]

Hi Icenowy,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tip/irq/core]
[also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.19-rc7 next-20260130]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Icenowy-Zheng/genirq-reserve-NR_IRQS_LEGACY-IRQs-in-dynirq-by-default/20260131-175403
base:   tip/irq/core
patch link:    https://lore.kernel.org/r/20260131094547.455916-6-zhengxingda%40iscas.ac.cn
patch subject: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code
config: loongarch-randconfig-001-20260201 (https://download.01.org/0day-ci/archive/20260202/202602020835.BnVM9ELe-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260202/202602020835.BnVM9ELe-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602020835.BnVM9ELe-lkp@intel.com/

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> WARNING: modpost: vmlinux: section mismatch in reference: pch_lpc_of_init+0x7c (section: .text.pch_lpc_of_init) -> pch_lpc_init (section: .init.text)

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for CAN_DEV
   Depends on [n]: NETDEVICES [=n] && CAN [=y]
   Selected by [y]:
   - CAN [=y] && NET [=y]

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 6/8] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64

[Icenowy Zheng]

As the driver can now support OF-based platforms, it's now possible to
use it on MIPS Loongson64 machines.

Drop the requirement of LOONGARCH for this driver, to allow build on
both MIPS-based and LoongArch-based Loongson systems.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f334f49c9791f..80a3ec2fc2aed 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -754,7 +754,6 @@ config LOONGSON_PCH_MSI
 
 config LOONGSON_PCH_LPC
 	bool "Loongson PCH LPC Controller"
-	depends on LOONGARCH
 	depends on MACH_LOONGSON64
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
-- 
2.52.0

[PATCH 7/8] MIPS: Loongson64: dts: sort nodes

[Icenowy Zheng]

The RTC's address is after UARTs, however the node is currently before
them.

Re-order the node to match address sequence.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index ee71045883e7e..5269bf0f789b0 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -19,13 +19,6 @@ pic: interrupt-controller@10000000 {
 			#interrupt-cells = <2>;
 		};
 
-		rtc0: rtc@100d0100 {
-			compatible = "loongson,ls7a-rtc";
-			reg = <0 0x100d0100 0 0x78>;
-			interrupt-parent = <&pic>;
-			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
 		ls7a_uart0: serial@10080000 {
 			compatible = "ns16550a";
 			reg = <0 0x10080000 0 0x100>;
@@ -65,6 +58,13 @@ ls7a_uart3: serial@10080300 {
 			no-loopback-test;
 		};
 
+		rtc0: rtc@100d0100 {
+			compatible = "loongson,ls7a-rtc";
+			reg = <0 0x100d0100 0 0x78>;
+			interrupt-parent = <&pic>;
+			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		pci@1a000000 {
 			compatible = "loongson,ls7a-pci";
 			device_type = "pci";
-- 
2.52.0

[PATCH 8/8] MIPS: Loongson64: dts: add node for LS7A PCH LPC

[Icenowy Zheng]

Loongson 7A series PCH contain a LPC IRQ controller.

Add the device tree node of it.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index 5269bf0f789b0..03018db47b18c 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -19,6 +19,15 @@ pic: interrupt-controller@10000000 {
 			#interrupt-cells = <2>;
 		};
 
+		lpc: interrupt-controller@10002000 {
+			compatible = "loongson,pch-lpc-1.0";
+			reg = <0 0x10002000 0 0x1000>;
+			interrupt-controller;
+			interrupt-parent = <&pic>;
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+		};
+
 		ls7a_uart0: serial@10080000 {
 			compatible = "ns16550a";
 			reg = <0 0x10080000 0 0x100>;
-- 
2.52.0

Re: [PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Yao Zi]

On Sat, Jan 31, 2026 at 05:45:39PM +0800, Icenowy Zheng wrote:
> This patchset tries to add support for Loongson 7A1000 PCH's LPC IRQ
> controller to MIPS-based Loongson systems.
> 
> LPC, from software's perspective of view, is just ISA, so the IRQs
> should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
> Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
> machines handled it, the setup is fragile and depends on its specific
> setup sequence (allocating the LPC IRQs first, and then allocate the
> parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
> breaks this fragile sequence, so the first commit is created to address
> for this issue (by reserving ISA IRQs from the dynamic IRQ allocation
> space).
> 
> Then the remaining commits are just adding OF(DT) based initialization
> of PCH LPC IRQ controller, like what happened on PCH PIC.
> 
> Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
> integrated ones. I don't own a LoongArch-based device with LPC
> peripherals, so test on LoongArch machines are welcomed.

Tested on TongFang L860-T2 system, which is LoongArch-based and exposes
keyboard and mouse as i8042, too. Nothing breaks with this series,

$ cat /proc/interrupts
           CPU0       CPU1       CPU2       CPU3
  1:        606          0          0          0  PCH LPC   1  i8042
 12:        645          0          0          0  PCH LPC  12  i8042
 20:      16393      14853      15443      17386  CPUINTC  12  IPI
 21:       4515       4154       3756       3701  CPUINTC  11  timer
 22:          0          0          0          0  PCH PIC   1  acpi
 28:          0          0          0          0  PCH PIC   7  loongson-alarm
 29:          0          0          0          0  PCH PIC   8  ls2x-i2c, ls2x-i2c, ls2x-i2c, ls2x-i2c, ls2x-i2c, ls2x-i2c
 37:          0          0          0          0 PCH-PCI-MSI-0000:00:09.0   0  PCIe bwctrl
 39:          0          0          0          0 PCH-PCI-MSI-0000:00:0a.0   0  PCIe bwctrl
 41:          0          0          0          0 PCH-PCI-MSI-0000:00:0b.0   0  PCIe bwctrl
 43:          0          0          0          0 PCH-PCI-MSI-0000:00:0c.0   0  PCIe bwctrl
 45:          0          0          0          0 PCH-PCI-MSI-0000:00:0d.0   0  PCIe bwctrl
 47:          0          0          0          0 PCH-PCI-MSI-0000:00:11.0   0  PCIe bwctrl
 49:          0          0          0          0 PCH-PCI-MSI-0000:00:13.0   0  PCIe bwctrl
 50:          0          0          0          0  PCH PIC  21  ahci[0000:00:08.0]
 51:         14          0          0          0 PCH-PCI-MSIX-0000:06:00.0   0  nvme0q0
 52:          0          0          0          0  PCH PIC  22  ahci[0000:00:08.1]
 53:          0          0          0          0  PCH PIC  23  ahci[0000:00:08.2]
 54:          0          0          0          0 PCH-PCI-MSI-0000:04:00.0   0  ahci[0000:04:00.0]
 55:        952          0          0          0 PCH-PCI-MSIX-0000:06:00.0   1  nvme0q1
 56:          0       1590          0          0 PCH-PCI-MSIX-0000:06:00.0   2  nvme0q2
 57:          0          0        916          0 PCH-PCI-MSIX-0000:06:00.0   3  nvme0q3
 58:          0          0          0       3836 PCH-PCI-MSIX-0000:06:00.0   4  nvme0q4
 61:       2649          0          0          0 PCH-PCI-MSI-0000:07:00.0   0  amdgpu
 62:       2561          0          0          0 PCH-PCI-MSI-0000:01:00.0   0  iwlwifi
IPI0:        350        507        573        311 LoongArch  1  Rescheduling interrupts
IPI1:      16044      14345      14870      17074 LoongArch  2  Function call interrupts
IPI2:          0          0          0          0 LoongArch  3  IRQ work interrupts
IPI3:          0          0          0          0 LoongArch  4  Clear vector interrupts
ERR:         12

Tested-by: Yao Zi <me@ziyao.cc>

Thanks for your work!

Regards,
Yao Zi