* [PATCH v4 0/2] PCI: Add support for ACS Enhanced Capability @ 2026-02-07 11:30 Wei Wang 2026-02-07 11:30 ` [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP Wei Wang 2026-02-07 11:30 ` [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() Wei Wang 0 siblings, 2 replies; 7+ messages in thread From: Wei Wang @ 2026-02-07 11:30 UTC (permalink / raw) To: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian Cc: linux-kernel, linux-pci, wei.w.wang This patchset adds support for the Access Control Services (ACS) Enhanced Capability, introduced with PCIe Gen 5. The ACS Enhanced Capability provides additional access control features that improve device isolation — particularly important in virtualization scenarios where devices are passed through to different virtual machines (VMs). Strong isolation is critical to ensure security between devices assigned to different VMs and the host. In Linux, device grouping assumes that devices in separate IOMMU groups are properly isolated. To uphold this assumption, the enhanced ACS controls are enabled by default on hardware that supports the PCI_ACS_ECAP capability. As with other basic ACS access controls, these new controls can be configured via the config_acs= boot parameter. Support for checking the enhanced ACS controls on Root and Downstream Ports has been added to pci_acs_enabled(). On devices that support PCI_ACS_ECAP, these controls must be properly enabled. To maintain compatibility with legacy devices that lack PCI_ACS_ECAP support, pci_acs_enabled() simply skips the check. v3->v4 changes: - In pci_acs_ecap_enabled(): Check the pcie type for PCI_EXP_TYPE_DOWNSTREAM explicitly. v3 Link: https://lore.kernel.org/all/SI2PR01MB439325B4E44D5A39F34A4015DC9AA@SI2PR01MB4393.apcprd01.prod.exchangelabs.com/ v2->v3 changes: - Drop the warning when a device has no support for the enhanced capability. v2 Link: https://lore.kernel.org/all/SI2PR01MB4393B836EA4FEDD1823483BADC94A@SI2PR01MB4393.apcprd01.prod.exchangelabs.com/ v1->v2 changes: - Enabled all enhanced ACS controls by default, rather than just Unclaimed Request Redirect (which addressed the primary issue we encountered). - Added checks for enhanced ACS controls on Root and Downstream Ports in pci_acs_enabled() to ensure proper enablement when grouping devices or enabling features such as IOMMU PASID. v1 Link: https://lore.kernel.org/all/SI2PR01MB43931A911357962A5E986FFEDC8CA@SI2PR01MB4393.apcprd01.prod.exchangelabs.com/ Thanks to Jason Gunthorpe for reviewing the patchset. Wei Wang (2): PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() .../admin-guide/kernel-parameters.txt | 23 ++++-- drivers/pci/pci.c | 78 ++++++++++++++++++- include/uapi/linux/pci_regs.h | 7 ++ 3 files changed, 100 insertions(+), 8 deletions(-) base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921 -- 2.51.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP 2026-02-07 11:30 [PATCH v4 0/2] PCI: Add support for ACS Enhanced Capability Wei Wang @ 2026-02-07 11:30 ` Wei Wang 2026-02-09 16:43 ` Jonathan Cameron 2026-02-07 11:30 ` [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() Wei Wang 1 sibling, 1 reply; 7+ messages in thread From: Wei Wang @ 2026-02-07 11:30 UTC (permalink / raw) To: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian Cc: linux-kernel, linux-pci, wei.w.wang The ACS Enhanced Capability introduces several new access controls to improve device isolation. These new controls are particularly important for device passthrough in virtualization scenarios. For example, a DMA transaction from a device may target a guest physical address that lies within the memory aperture of the switch's upstream port, but not within any memory aperture or BAR space of a downstream port. In such cases, the switch would generate an Unsupported Request (UR) response to the device, which is undesirable. Enabling Unclaimed Request Redirect Control ensures that these DMA requests are forwarded upstream instead of being rejected. The ACS DSP and USP Memory Target Access Control and ACS I/O Request Blocking features similarly enhance device isolation. Device grouping in Linux assumes that devices are properly isolated. Therefore, enable these controls by default if PCI_ACS_ECAP is supported by the hardware. As with other basic ACS access controls, these new controls can be configured via the "config_acs = " boot parameter. Signed-off-by: Wei Wang <wei.w.wang@hotmail.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> --- .../admin-guide/kernel-parameters.txt | 23 +++++++++++++------ drivers/pci/pci.c | 13 ++++++++++- include/uapi/linux/pci_regs.h | 7 ++++++ 3 files changed, 35 insertions(+), 8 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 7cfbf1102152..fd895716b07d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5301,13 +5301,22 @@ Kernel parameters flags. ACS Flags is defined as follows: - bit-0 : ACS Source Validation - bit-1 : ACS Translation Blocking - bit-2 : ACS P2P Request Redirect - bit-3 : ACS P2P Completion Redirect - bit-4 : ACS Upstream Forwarding - bit-5 : ACS P2P Egress Control - bit-6 : ACS Direct Translated P2P + bit-0 : ACS Source Validation + bit-1 : ACS Translation Blocking + bit-2 : ACS P2P Request Redirect + bit-3 : ACS P2P Completion Redirect + bit-4 : ACS Upstream Forwarding + bit-5 : ACS P2P Egress Control + bit-6 : ACS Direct Translated P2P + bit-7 : ACS I/O Request Blocking + bit-9:8 : ACS DSP Memory Target Access Ctrl + 00 : Direct Request access enabled + 01 : Request blocking enabled + 10 : Request redirect enabled + 11 : Reserved + bit-11:10 : ACS USP Memory Target Access Ctrl + Same encoding as bit-9:8 + bit-12 : ACS Unclaimed Request Redirect Ctrl Each bit can be marked as: '0' – force disabled '1' – force enabled diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d2810eb97bda..1714e29ce099 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -942,7 +942,10 @@ static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps, } if (mask & ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | PCI_ACS_CR | - PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT)) { + PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT | PCI_ACS_IB | + PCI_ACS_DMAC_RB | PCI_ACS_DMAC_RR | + PCI_ACS_UMAC_RB | PCI_ACS_UMAC_RR | + PCI_ACS_URRC)) { pci_err(dev, "Invalid ACS flags specified\n"); return; } @@ -1002,6 +1005,14 @@ static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps) /* Upstream Forwarding */ caps->ctrl |= (caps->cap & PCI_ACS_UF); + /* + * Downstream and Upstream Port Memory Target Access Redirect, + * Redirect Unclaimed Request Redirect Control + */ + if (caps->cap & PCI_ACS_ECAP) + caps->ctrl |= PCI_ACS_DMAC_RR | PCI_ACS_UMAC_RR | + PCI_ACS_URRC | PCI_ACS_IB; + /* Enable Translation Blocking for external devices and noats */ if (pci_ats_disabled() || dev->external_facing || dev->untrusted) caps->ctrl |= (caps->cap & PCI_ACS_TB); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ec1c54b5a310..593ef522d2ba 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1016,6 +1016,7 @@ /* Access Control Service */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ +#define PCI_ACS_ECAP 0x0080 /* ACS Enhanced Capability */ #define PCI_ACS_SV 0x0001 /* Source Validation */ #define PCI_ACS_TB 0x0002 /* Translation Blocking */ #define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ @@ -1023,6 +1024,12 @@ #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ +#define PCI_ACS_IB 0x0080 /* I/O Request Blocking */ +#define PCI_ACS_DMAC_RB 0x0100 /* DSP Memory Target Access Blocking */ +#define PCI_ACS_DMAC_RR 0x0200 /* DSP Memory Target Access Redirect */ +#define PCI_ACS_UMAC_RB 0x0400 /* USP Memory Target Access Blocking */ +#define PCI_ACS_UMAC_RR 0x0800 /* USP Memory Target Access Redirect */ +#define PCI_ACS_URRC 0x1000 /* Unclaimed Request Redirect Ctrl */ #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ -- 2.51.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP 2026-02-07 11:30 ` [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP Wei Wang @ 2026-02-09 16:43 ` Jonathan Cameron 2026-02-10 15:02 ` Wei Wang 0 siblings, 1 reply; 7+ messages in thread From: Jonathan Cameron @ 2026-02-09 16:43 UTC (permalink / raw) To: Wei Wang Cc: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian, linux-kernel, linux-pci On Sat, 7 Feb 2026 19:30:58 +0800 Wei Wang <wei.w.wang@hotmail.com> wrote: > The ACS Enhanced Capability introduces several new access controls to > improve device isolation. These new controls are particularly important > for device passthrough in virtualization scenarios. > > For example, a DMA transaction from a device may target a guest physical > address that lies within the memory aperture of the switch's upstream > port, but not within any memory aperture or BAR space of a downstream > port. In such cases, the switch would generate an Unsupported Request (UR) > response to the device, which is undesirable. Enabling Unclaimed Request > Redirect Control ensures that these DMA requests are forwarded upstream > instead of being rejected. > > The ACS DSP and USP Memory Target Access Control and ACS I/O Request > Blocking features similarly enhance device isolation. Device grouping in > Linux assumes that devices are properly isolated. Therefore, enable these > controls by default if PCI_ACS_ECAP is supported by the hardware. As with > other basic ACS access controls, these new controls can be configured via > the "config_acs = " boot parameter. > > Signed-off-by: Wei Wang <wei.w.wang@hotmail.com> > Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Hi Wei Wang, I'm late to the game here and may be missing something but I think the validation and defines for the 2 bit fields are both misleading and not sufficiently careful to reject values that are not allowed. Maybe we do want to allow the reserved value but if so use a 2 bit mask to validate, not two specific values that the filed can take. Thanks, Jonathan > --- > .../admin-guide/kernel-parameters.txt | 23 +++++++++++++------ > drivers/pci/pci.c | 13 ++++++++++- > include/uapi/linux/pci_regs.h | 7 ++++++ > 3 files changed, 35 insertions(+), 8 deletions(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 7cfbf1102152..fd895716b07d 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -5301,13 +5301,22 @@ Kernel parameters > flags. > > ACS Flags is defined as follows: > - bit-0 : ACS Source Validation > - bit-1 : ACS Translation Blocking > - bit-2 : ACS P2P Request Redirect > - bit-3 : ACS P2P Completion Redirect > - bit-4 : ACS Upstream Forwarding > - bit-5 : ACS P2P Egress Control > - bit-6 : ACS Direct Translated P2P > + bit-0 : ACS Source Validation > + bit-1 : ACS Translation Blocking > + bit-2 : ACS P2P Request Redirect > + bit-3 : ACS P2P Completion Redirect > + bit-4 : ACS Upstream Forwarding > + bit-5 : ACS P2P Egress Control > + bit-6 : ACS Direct Translated P2P > + bit-7 : ACS I/O Request Blocking > + bit-9:8 : ACS DSP Memory Target Access Ctrl > + 00 : Direct Request access enabled > + 01 : Request blocking enabled > + 10 : Request redirect enabled > + 11 : Reserved > + bit-11:10 : ACS USP Memory Target Access Ctrl > + Same encoding as bit-9:8 > + bit-12 : ACS Unclaimed Request Redirect Ctrl > Each bit can be marked as: > '0' – force disabled > '1' – force enabled > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index d2810eb97bda..1714e29ce099 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -942,7 +942,10 @@ static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps, > } > > if (mask & ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | PCI_ACS_CR | > - PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT)) { > + PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT | PCI_ACS_IB | > + PCI_ACS_DMAC_RB | PCI_ACS_DMAC_RR | > + PCI_ACS_UMAC_RB | PCI_ACS_UMAC_RR | > + PCI_ACS_URRC)) { This used of the RB and RR Bits seems misleading to me as they form parts of 2 bit field that can only take values 0, 1 and 2. So if the command line set PCI_ACS_UMAC_RB and PCI_ACS_UMAC_RR it would have hit the reserved value and that should be detected. Hence I think you need to do this sort of masking + additional checks that these 2 bit fields have valid content. > pci_err(dev, "Invalid ACS flags specified\n"); > return; > } > @@ -1002,6 +1005,14 @@ static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps) > /* Upstream Forwarding */ > caps->ctrl |= (caps->cap & PCI_ACS_UF); > > + /* > + * Downstream and Upstream Port Memory Target Access Redirect, > + * Redirect Unclaimed Request Redirect Control > + */ > + if (caps->cap & PCI_ACS_ECAP) > + caps->ctrl |= PCI_ACS_DMAC_RR | PCI_ACS_UMAC_RR | > + PCI_ACS_URRC | PCI_ACS_IB; > + > /* Enable Translation Blocking for external devices and noats */ > if (pci_ats_disabled() || dev->external_facing || dev->untrusted) > caps->ctrl |= (caps->cap & PCI_ACS_TB); > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index ec1c54b5a310..593ef522d2ba 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1016,6 +1016,7 @@ > > /* Access Control Service */ > #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ > +#define PCI_ACS_ECAP 0x0080 /* ACS Enhanced Capability */ > #define PCI_ACS_SV 0x0001 /* Source Validation */ > #define PCI_ACS_TB 0x0002 /* Translation Blocking */ > #define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ > @@ -1023,6 +1024,12 @@ > #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ > #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ > #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ > +#define PCI_ACS_IB 0x0080 /* I/O Request Blocking */ > +#define PCI_ACS_DMAC_RB 0x0100 /* DSP Memory Target Access Blocking */ > +#define PCI_ACS_DMAC_RR 0x0200 /* DSP Memory Target Access Redirect */ > +#define PCI_ACS_UMAC_RB 0x0400 /* USP Memory Target Access Blocking */ If I'm reading this write, those are specific values in the ACS USP Memory Target Access Control, not what they appear to be here which is bits that can be combined. I think you need a _MASK and separate definitions for the 3 values that are allowed. > +#define PCI_ACS_UMAC_RR 0x0800 /* USP Memory Target Access Redirect */ > +#define PCI_ACS_URRC 0x1000 /* Unclaimed Request Redirect Ctrl */ > #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ > #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ > #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP 2026-02-09 16:43 ` Jonathan Cameron @ 2026-02-10 15:02 ` Wei Wang 0 siblings, 0 replies; 7+ messages in thread From: Wei Wang @ 2026-02-10 15:02 UTC (permalink / raw) To: Jonathan Cameron Cc: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian, linux-kernel, linux-pci On 2/10/26 12:43 AM, Jonathan Cameron wrote: > On Sat, 7 Feb 2026 19:30:58 +0800 > Wei Wang <wei.w.wang@hotmail.com> wrote: > >> The ACS Enhanced Capability introduces several new access controls to >> improve device isolation. These new controls are particularly important >> for device passthrough in virtualization scenarios. >> >> For example, a DMA transaction from a device may target a guest physical >> address that lies within the memory aperture of the switch's upstream >> port, but not within any memory aperture or BAR space of a downstream >> port. In such cases, the switch would generate an Unsupported Request (UR) >> response to the device, which is undesirable. Enabling Unclaimed Request >> Redirect Control ensures that these DMA requests are forwarded upstream >> instead of being rejected. >> >> The ACS DSP and USP Memory Target Access Control and ACS I/O Request >> Blocking features similarly enhance device isolation. Device grouping in >> Linux assumes that devices are properly isolated. Therefore, enable these >> controls by default if PCI_ACS_ECAP is supported by the hardware. As with >> other basic ACS access controls, these new controls can be configured via >> the "config_acs = " boot parameter. >> >> Signed-off-by: Wei Wang <wei.w.wang@hotmail.com> >> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> > > Hi Wei Wang, > > I'm late to the game here and may be missing something but > I think the validation and defines for the 2 bit fields are both > misleading and not sufficiently careful to reject values that > are not allowed. Maybe we do want to allow the reserved value > but if so use a 2 bit mask to validate, not two specific > values that the filed can take. > Hi Jonathan, Thanks for your comments. Yes, I think it's better to reject the reserved encoding (0b11). I'll add masks and enum values for the encodings, and validate that the value is not 0b11. #define PCI_ACS_DMAC_MASK 0x0300 #define PCI_ACS_UMAC_MASK 0x0C00 enum { PCI_ACS_MAC_DA = 0x0, PCI_ACS_MAC_RB = 0x1, PCI_ACS_MAC_RR = 0x2, PCI_ACS_MAC_RSVD = 0x3, }; > Thanks, > > Jonathan > >> --- >> .../admin-guide/kernel-parameters.txt | 23 +++++++++++++------ >> drivers/pci/pci.c | 13 ++++++++++- >> include/uapi/linux/pci_regs.h | 7 ++++++ >> 3 files changed, 35 insertions(+), 8 deletions(-) >> >> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt >> index 7cfbf1102152..fd895716b07d 100644 >> --- a/Documentation/admin-guide/kernel-parameters.txt >> +++ b/Documentation/admin-guide/kernel-parameters.txt >> @@ -5301,13 +5301,22 @@ Kernel parameters >> flags. >> >> ACS Flags is defined as follows: >> - bit-0 : ACS Source Validation >> - bit-1 : ACS Translation Blocking >> - bit-2 : ACS P2P Request Redirect >> - bit-3 : ACS P2P Completion Redirect >> - bit-4 : ACS Upstream Forwarding >> - bit-5 : ACS P2P Egress Control >> - bit-6 : ACS Direct Translated P2P >> + bit-0 : ACS Source Validation >> + bit-1 : ACS Translation Blocking >> + bit-2 : ACS P2P Request Redirect >> + bit-3 : ACS P2P Completion Redirect >> + bit-4 : ACS Upstream Forwarding >> + bit-5 : ACS P2P Egress Control >> + bit-6 : ACS Direct Translated P2P >> + bit-7 : ACS I/O Request Blocking >> + bit-9:8 : ACS DSP Memory Target Access Ctrl >> + 00 : Direct Request access enabled >> + 01 : Request blocking enabled >> + 10 : Request redirect enabled >> + 11 : Reserved >> + bit-11:10 : ACS USP Memory Target Access Ctrl >> + Same encoding as bit-9:8 >> + bit-12 : ACS Unclaimed Request Redirect Ctrl >> Each bit can be marked as: >> '0' – force disabled >> '1' – force enabled >> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c >> index d2810eb97bda..1714e29ce099 100644 >> --- a/drivers/pci/pci.c >> +++ b/drivers/pci/pci.c >> @@ -942,7 +942,10 @@ static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps, >> } >> >> if (mask & ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | PCI_ACS_CR | >> - PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT)) { >> + PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT | PCI_ACS_IB | >> + PCI_ACS_DMAC_RB | PCI_ACS_DMAC_RR | >> + PCI_ACS_UMAC_RB | PCI_ACS_UMAC_RR | >> + PCI_ACS_URRC)) { > This used of the RB and RR Bits seems misleading to me as they form parts > of 2 bit field that can only take values 0, 1 and 2. > > So if the command line set PCI_ACS_UMAC_RB and PCI_ACS_UMAC_RR it > would have hit the reserved value and that should be detected. > > Hence I think you need to do this sort of masking + additional checks that these > 2 bit fields have valid content. Yes, will do. > >> pci_err(dev, "Invalid ACS flags specified\n"); >> return; >> } >> @@ -1002,6 +1005,14 @@ static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps) >> /* Upstream Forwarding */ >> caps->ctrl |= (caps->cap & PCI_ACS_UF); >> >> + /* >> + * Downstream and Upstream Port Memory Target Access Redirect, >> + * Redirect Unclaimed Request Redirect Control >> + */ >> + if (caps->cap & PCI_ACS_ECAP) >> + caps->ctrl |= PCI_ACS_DMAC_RR | PCI_ACS_UMAC_RR | >> + PCI_ACS_URRC | PCI_ACS_IB; >> + >> /* Enable Translation Blocking for external devices and noats */ >> if (pci_ats_disabled() || dev->external_facing || dev->untrusted) >> caps->ctrl |= (caps->cap & PCI_ACS_TB); >> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >> index ec1c54b5a310..593ef522d2ba 100644 >> --- a/include/uapi/linux/pci_regs.h >> +++ b/include/uapi/linux/pci_regs.h >> @@ -1016,6 +1016,7 @@ >> >> /* Access Control Service */ >> #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ >> +#define PCI_ACS_ECAP 0x0080 /* ACS Enhanced Capability */ >> #define PCI_ACS_SV 0x0001 /* Source Validation */ >> #define PCI_ACS_TB 0x0002 /* Translation Blocking */ >> #define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ >> @@ -1023,6 +1024,12 @@ >> #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ >> #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ >> #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ >> +#define PCI_ACS_IB 0x0080 /* I/O Request Blocking */ >> +#define PCI_ACS_DMAC_RB 0x0100 /* DSP Memory Target Access Blocking */ >> +#define PCI_ACS_DMAC_RR 0x0200 /* DSP Memory Target Access Redirect */ >> +#define PCI_ACS_UMAC_RB 0x0400 /* USP Memory Target Access Blocking */ > > If I'm reading this write, those are specific values in the > ACS USP Memory Target Access Control, not what they appear to be here > which is bits that can be combined. > I think you need a _MASK and separate definitions for the 3 values that > are allowed. Yes. > >> +#define PCI_ACS_UMAC_RR 0x0800 /* USP Memory Target Access Redirect */ >> +#define PCI_ACS_URRC 0x1000 /* Unclaimed Request Redirect Ctrl */ >> #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ >> #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ >> #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() 2026-02-07 11:30 [PATCH v4 0/2] PCI: Add support for ACS Enhanced Capability Wei Wang 2026-02-07 11:30 ` [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP Wei Wang @ 2026-02-07 11:30 ` Wei Wang 2026-02-09 16:50 ` Jonathan Cameron 1 sibling, 1 reply; 7+ messages in thread From: Wei Wang @ 2026-02-07 11:30 UTC (permalink / raw) To: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian Cc: linux-kernel, linux-pci, wei.w.wang The enhanced ACS controls introduced by PCIe Gen 5 ensures better device isolation. On devices that support the PCI_ACS_ECAP capability, the controls are required to be enabled properly: - ACS I/O Request Blocking needs to be enabled to avoid unintended upstream I/O requests. - ACS DSP and USP Memory Target Access Control needs to be set with Request Redirect or Request Blocking to ensure the Downstream and Upstream Port memory resource ranges are not accessed by upstream memory requests. - ACS Unclaimed Request Redirect needs to be enabled to ensure accesses to areas that lies within a Switch's Upstream Port memory apertures but not within any Downstream Port memory apertures get redirected. To maintain compatibility with legacy devices that lack PCI_ACS_ECAP support, pci_acs_enabled() skips checking for the capability. Signed-off-by: Wei Wang <wei.w.wang@hotmail.com> --- drivers/pci/pci.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1714e29ce099..53e79948b4ea 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3527,6 +3527,56 @@ void pci_configure_ari(struct pci_dev *dev) } } +static bool pci_dev_has_memory_bars(struct pci_dev *pdev) +{ + int i; + + for (i = 0; i <= PCI_ROM_RESOURCE; i++) { + if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) + return true; + } + + return false; +} + +static bool pci_acs_ecap_enabled(struct pci_dev *pdev, u16 ctrl) +{ + bool is_dsp = pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM; + struct pci_dev *usp_pdev = pci_upstream_bridge(pdev); + u16 mask = PCI_ACS_DMAC_RB | PCI_ACS_DMAC_RR; + + /* + * For ACS DSP/USP Memory Target Access Control, either Request + * Redirect or Request Blocking must be enabled to enforce isolation. + * According to PCIe spec 7.0, the DSP Memory Target Access is + * applicable to both Root Ports and Switch Upstream Ports that have + * applicable Memory BAR space to protect. So if the device does not + * have a Memory BAR, it skips the check. + */ + if (pci_dev_has_memory_bars(pdev) && + (ctrl & mask) != PCI_ACS_DMAC_RB && + (ctrl & mask) != PCI_ACS_DMAC_RR) + return false; + + mask = PCI_ACS_UMAC_RB | PCI_ACS_UMAC_RR; + /* + * The USP Memory Target Access is only applicable to downstream ports + * that have applicable Memory BAR space in the Switch Upstream Port to + * protect. + */ + if (is_dsp && pci_dev_has_memory_bars(usp_pdev) && + (ctrl & mask) != PCI_ACS_UMAC_RB && + (ctrl & mask) != PCI_ACS_UMAC_RR) + return false; + + /* PCI_ACS_URRC is applicable to Downstream Ports only. */ + if (is_dsp && !(ctrl & PCI_ACS_URRC)) + return false; + + /* PCI_ACS_IB is applicable to both Root and Downstream Ports. */ + return !!(ctrl & PCI_ACS_IB); +} + static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) { int pos; @@ -3545,6 +3595,19 @@ static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) acs_flags &= (cap | PCI_ACS_EC); pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); + + if (acs_flags & PCI_ACS_ECAP) { + if ((cap & PCI_ACS_ECAP) && !pci_acs_ecap_enabled(pdev, ctrl)) + return false; + + /* + * The check for the required controls in PCI_ACS_ECAP has + * passed. Clear the ECAP flag and continue to check the + * basic ACS controls. + */ + acs_flags &= ~PCI_ACS_ECAP; + } + return (ctrl & acs_flags) == acs_flags; } @@ -3603,6 +3666,8 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) */ case PCI_EXP_TYPE_DOWNSTREAM: case PCI_EXP_TYPE_ROOT_PORT: + /* PCI_ACS_ECAP applies to Root and Downstream Ports only */ + acs_flags |= PCI_ACS_ECAP; return pci_acs_flags_enabled(pdev, acs_flags); /* * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be -- 2.51.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() 2026-02-07 11:30 ` [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() Wei Wang @ 2026-02-09 16:50 ` Jonathan Cameron 2026-02-10 15:06 ` Wei Wang 0 siblings, 1 reply; 7+ messages in thread From: Jonathan Cameron @ 2026-02-09 16:50 UTC (permalink / raw) To: Wei Wang Cc: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian, linux-kernel, linux-pci On Sat, 7 Feb 2026 19:30:59 +0800 Wei Wang <wei.w.wang@hotmail.com> wrote: > The enhanced ACS controls introduced by PCIe Gen 5 ensures better device > isolation. On devices that support the PCI_ACS_ECAP capability, the > controls are required to be enabled properly: > - ACS I/O Request Blocking needs to be enabled to avoid unintended > upstream I/O requests. > - ACS DSP and USP Memory Target Access Control needs to be set with > Request Redirect or Request Blocking to ensure the Downstream and > Upstream Port memory resource ranges are not accessed by upstream > memory requests. > - ACS Unclaimed Request Redirect needs to be enabled to ensure accesses to > areas that lies within a Switch's Upstream Port memory apertures but not > within any Downstream Port memory apertures get redirected. > > To maintain compatibility with legacy devices that lack PCI_ACS_ECAP > support, pci_acs_enabled() skips checking for the capability. > > Signed-off-by: Wei Wang <wei.w.wang@hotmail.com> Hi Wei Wang, A few things inline. Thanks, Jonathan > --- > drivers/pci/pci.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 1714e29ce099..53e79948b4ea 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > +static bool pci_acs_ecap_enabled(struct pci_dev *pdev, u16 ctrl) > +{ > + bool is_dsp = pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM; > + struct pci_dev *usp_pdev = pci_upstream_bridge(pdev); > + u16 mask = PCI_ACS_DMAC_RB | PCI_ACS_DMAC_RR; > + > + /* > + * For ACS DSP/USP Memory Target Access Control, either Request > + * Redirect or Request Blocking must be enabled to enforce isolation. > + * According to PCIe spec 7.0, the DSP Memory Target Access is > + * applicable to both Root Ports and Switch Upstream Ports that have > + * applicable Memory BAR space to protect. So if the device does not > + * have a Memory BAR, it skips the check. > + */ > + if (pci_dev_has_memory_bars(pdev) && > + (ctrl & mask) != PCI_ACS_DMAC_RB && > + (ctrl & mask) != PCI_ACS_DMAC_RR) As below. I'd use the mask define suggested in previous then FIELD_GET() plus checking the value of that against defines for these two field values. > + return false; > + > + mask = PCI_ACS_UMAC_RB | PCI_ACS_UMAC_RR; This is the mask for the field that should be in the header. > + /* > + * The USP Memory Target Access is only applicable to downstream ports > + * that have applicable Memory BAR space in the Switch Upstream Port to > + * protect. > + */ > + if (is_dsp && pci_dev_has_memory_bars(usp_pdev) && > + (ctrl & mask) != PCI_ACS_UMAC_RB && > + (ctrl & mask) != PCI_ACS_UMAC_RR) > + return false; > + > + /* PCI_ACS_URRC is applicable to Downstream Ports only. */ > + if (is_dsp && !(ctrl & PCI_ACS_URRC)) > + return false; I'd be tempted to group the DSP specific handling and drop the local variable. if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) { if (pci_dev_has_memory_bars(usp_pdev) && (ctrl & mask) != PCI_ACS_UMAC_RB && (ctrl & mask) != PCI_ACS_UMAC_RR) // or use FIELD_GET() to get using the mask suggested in previous patch then // match what was in the filed here. return false; if (!(ctrl & PCI_ACS_URRC)) return false; } > + > + /* PCI_ACS_IB is applicable to both Root and Downstream Ports. */ > + return !!(ctrl & PCI_ACS_IB); > +} > + ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() 2026-02-09 16:50 ` Jonathan Cameron @ 2026-02-10 15:06 ` Wei Wang 0 siblings, 0 replies; 7+ messages in thread From: Wei Wang @ 2026-02-10 15:06 UTC (permalink / raw) To: Jonathan Cameron Cc: bhelgaas, jgg, akpm, bp, rdunlap, alex, kevin.tian, linux-kernel, linux-pci On 2/10/26 12:50 AM, Jonathan Cameron wrote: >> + /* >> + * The USP Memory Target Access is only applicable to downstream ports >> + * that have applicable Memory BAR space in the Switch Upstream Port to >> + * protect. >> + */ >> + if (is_dsp && pci_dev_has_memory_bars(usp_pdev) && >> + (ctrl & mask) != PCI_ACS_UMAC_RB && >> + (ctrl & mask) != PCI_ACS_UMAC_RR) >> + return false; >> + >> + /* PCI_ACS_URRC is applicable to Downstream Ports only. */ >> + if (is_dsp && !(ctrl & PCI_ACS_URRC)) >> + return false; > > I'd be tempted to group the DSP specific handling and drop the local variable. > > if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) { > if (pci_dev_has_memory_bars(usp_pdev) && > (ctrl & mask) != PCI_ACS_UMAC_RB && > (ctrl & mask) != PCI_ACS_UMAC_RR) > // or use FIELD_GET() to get using the mask suggested in previous patch then > // match what was in the filed here. Sounds good, thanks. ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-02-10 15:08 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-02-07 11:30 [PATCH v4 0/2] PCI: Add support for ACS Enhanced Capability Wei Wang 2026-02-07 11:30 ` [PATCH v4 1/2] PCI: Enable the enhanced ACS controls introduced by PCI_ACS_ECAP Wei Wang 2026-02-09 16:43 ` Jonathan Cameron 2026-02-10 15:02 ` Wei Wang 2026-02-07 11:30 ` [PATCH v4 2/2] PCI: Add the enhanced ACS controls check to pci_acs_flags_enabled() Wei Wang 2026-02-09 16:50 ` Jonathan Cameron 2026-02-10 15:06 ` Wei Wang
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