* [PATCH v4 1/4] dt-bindings: soc: rockchip: grf: Add RV1103B compatibles
@ 2026-02-11 11:05 Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 2/4] ARM: dts: rockchip: Add support for RV1103B Fabio Estevam
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Fabio Estevam @ 2026-02-11 11:05 UTC (permalink / raw)
To: heiko
Cc: jonas, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Fabio Estevam, Krzysztof Kozlowski
From: Fabio Estevam <festevam@nabladev.com>
Add the PMU GRF and IOC compatible strings for the RV1103B SoC.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Changes since v3:
- None.
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 0b8e3294c83e..2cc43742b8e3 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -63,6 +63,7 @@ properties:
- rockchip,rk3588-vo0-grf
- rockchip,rk3588-vo1-grf
- rockchip,rk3588-vop-grf
+ - rockchip,rv1103b-ioc
- rockchip,rv1108-usbgrf
- const: syscon
- items:
@@ -98,6 +99,7 @@ properties:
- rockchip,rk3576-pmu0-grf
- rockchip,rk3576-usb2phy-grf
- rockchip,rk3588-usb2phy-grf
+ - rockchip,rv1103b-pmu-grf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
- rockchip,rv1126-grf
@@ -231,6 +233,7 @@ allOf:
- rockchip,rk3036-grf
- rockchip,rk3308-grf
- rockchip,rk3368-pmugrf
+ - rockchip,rv1103b-pmu-grf
then:
properties:
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v4 2/4] ARM: dts: rockchip: Add support for RV1103B
2026-02-11 11:05 [PATCH v4 1/4] dt-bindings: soc: rockchip: grf: Add RV1103B compatibles Fabio Estevam
@ 2026-02-11 11:05 ` Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 3/4] dt-bindings: arm: rockchip: Add Omega4 Evaluation board Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 4/4] ARM: dts: rockchip: Add Onion Omega4 Evaluation Board Fabio Estevam
2 siblings, 0 replies; 4+ messages in thread
From: Fabio Estevam @ 2026-02-11 11:05 UTC (permalink / raw)
To: heiko
Cc: jonas, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add the initial RV1103B devicetree.
Based on the 5.10 Rockchip vendor kernel.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
The <dt-bindings/clock/rockchip,rv1103b-cru.h> header comes from another
series:
https://lore.kernel.org/linux-devicetree/20260210022620.172570-1-festevam@gmail.com/
Maybe Heiko could apply the clock series as well?
Changes since v3:
- Do not use _ in container name.
- Remove reference to internal vendor tool.
- Move memory mapped peripherals inside soc node.
- Remove unnecesay extra pinctrl entry.
.../boot/dts/rockchip/rv1103b-pinctrl.dtsi | 816 ++++++++++++++++++
arch/arm/boot/dts/rockchip/rv1103b.dtsi | 257 ++++++
2 files changed, 1073 insertions(+)
create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rockchip/rv1103b.dtsi
diff --git a/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
new file mode 100644
index 000000000000..539d4d9510c1
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
@@ -0,0 +1,816 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+&pinctrl {
+ cam-clk0 {
+ /omit-if-no-ref/
+ cam_clk0: cam-clk0 {
+ rockchip,pins =
+ /* cam_clk0_out */
+ <1 RK_PB5 1 &pcfg_pull_none>;
+ };
+ };
+
+ cam-clk1 {
+ /omit-if-no-ref/
+ cam_clk1: cam-clk1 {
+ rockchip,pins =
+ /* cam_clk1_out */
+ <1 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ cam-spi {
+ /omit-if-no-ref/
+ cam_spi_bus4: cam-spi-bus4 {
+ rockchip,pins =
+ /* cam_spi_d0 */
+ <0 RK_PB5 4 &pcfg_pull_up_drv_level_2>,
+ /* cam_spi_d1 */
+ <0 RK_PB2 4 &pcfg_pull_up_drv_level_2>,
+ /* cam_spi_d2 */
+ <0 RK_PB1 4 &pcfg_pull_up_drv_level_2>,
+ /* cam_spi_d3 */
+ <0 RK_PB0 4 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ cam_spi_clk: cam-spi-clk {
+ rockchip,pins =
+ /* cam_spi_clk */
+ <0 RK_PB4 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ cam_spi_cs0n: cam-spi-cs0n {
+ rockchip,pins =
+ /* cam_spi_cs0n */
+ <0 RK_PB3 4 &pcfg_pull_none>;
+ };
+ };
+
+ clk {
+ /omit-if-no-ref/
+ clk_32k: clk-32k {
+ rockchip,pins =
+ /* clk_32k */
+ <0 RK_PA0 2 &pcfg_pull_none>;
+ };
+ };
+
+ clk-24m {
+ /omit-if-no-ref/
+ clk_24m_out: clk-24m-out {
+ rockchip,pins =
+ /* clk_24m_out */
+ <0 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ /omit-if-no-ref/
+ cpu: cpu {
+ rockchip,pins =
+ /* cpu_avs */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspi_bus4: fspi-bus4 {
+ rockchip,pins =
+ /* fspi_d0 */
+ <1 RK_PA1 2 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PA2 2 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PA3 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PA0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi_cs0: fspi-cs0 {
+ rockchip,pins =
+ /* fspi_cs0n */
+ <1 RK_PA5 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ fspi_clk: fspi-clk {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PA4 2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <0 RK_PA5 3 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <0 RK_PA6 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <1 RK_PB4 5 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <1 RK_PB3 5 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m2_xfer: i2c0m2-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m2 */
+ <1 RK_PB5 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m2 */
+ <1 RK_PB6 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB0 1 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB1 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <2 RK_PA4 4 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <2 RK_PA5 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PB2 1 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PB3 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <2 RK_PA6 4 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <2 RK_PA7 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <0 RK_PB4 1 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <0 RK_PB5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <2 RK_PB3 4 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <2 RK_PB2 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <2 RK_PB0 4 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m0 */
+ <2 RK_PB1 4 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <1 RK_PB7 2 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m1 */
+ <1 RK_PC0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0: jtagm0 {
+ rockchip,pins =
+ /* jtag_tck_m0 */
+ <0 RK_PA5 5 &pcfg_pull_none>,
+ /* jtag_tms_m0 */
+ <0 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1: jtagm1 {
+ rockchip,pins =
+ /* jtag_tck_m1 */
+ <0 RK_PB4 3 &pcfg_pull_none>,
+ /* jtag_tms_m1 */
+ <0 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm2: jtagm2 {
+ rockchip,pins =
+ /* jtag_tck_m2 */
+ <1 RK_PB4 3 &pcfg_pull_none>,
+ /* jtag_tms_m2 */
+ <1 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ psram-spi {
+ /omit-if-no-ref/
+ psram_spi_bus4: psram-spi-bus4 {
+ rockchip,pins =
+ /* psram_spi_d0 */
+ <0 RK_PA2 4 &pcfg_pull_none>,
+ /* psram_spi_d1 */
+ <0 RK_PA1 4 &pcfg_pull_none>,
+ /* psram_spi_d2 */
+ <0 RK_PA5 4 &pcfg_pull_none>,
+ /* psram_spi_d3 */
+ <0 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ psram_spi_clk: psram-spi-clk {
+ rockchip,pins =
+ /* psram_spi_clk */
+ <0 RK_PA0 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ psram_spi_cs0n: psram-spi-cs0n {
+ rockchip,pins =
+ /* psram_spi_cs0n */
+ <0 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_ch0: pwm0m0-ch0 {
+ rockchip,pins =
+ /* pwm0m0_ch0 */
+ <0 RK_PA1 1 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m0_ch1: pwm0m0-ch1 {
+ rockchip,pins =
+ /* pwm0m0_ch1 */
+ <0 RK_PA5 2 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m0_ch2: pwm0m0-ch2 {
+ rockchip,pins =
+ /* pwm0m0_ch2 */
+ <0 RK_PA6 2 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m0_ch3: pwm0m0-ch3 {
+ rockchip,pins =
+ /* pwm0m0_ch3 */
+ <0 RK_PA2 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_ch0: pwm0m1-ch0 {
+ rockchip,pins =
+ /* pwm0m1_ch0 */
+ <2 RK_PA0 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m1_ch1: pwm0m1-ch1 {
+ rockchip,pins =
+ /* pwm0m1_ch1 */
+ <2 RK_PA1 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m1_ch2: pwm0m1-ch2 {
+ rockchip,pins =
+ /* pwm0m1_ch2 */
+ <2 RK_PA2 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m1_ch3: pwm0m1-ch3 {
+ rockchip,pins =
+ /* pwm0m1_ch3 */
+ <2 RK_PB0 3 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_ch1: pwm0m2-ch1 {
+ rockchip,pins =
+ /* pwm0m2_ch1 */
+ <1 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm0m2_ch2: pwm0m2-ch2 {
+ rockchip,pins =
+ /* pwm0m2_ch2 */
+ <1 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_ch0: pwm1m0-ch0 {
+ rockchip,pins =
+ /* pwm1m0_ch0 */
+ <0 RK_PB0 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm1m0_ch1: pwm1m0-ch1 {
+ rockchip,pins =
+ /* pwm1m0_ch1 */
+ <0 RK_PB1 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm1m0_ch2: pwm1m0-ch2 {
+ rockchip,pins =
+ /* pwm1m0_ch2 */
+ <0 RK_PB2 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm1m0_ch3: pwm1m0-ch3 {
+ rockchip,pins =
+ /* pwm1m0_ch3 */
+ <0 RK_PB3 3 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch0: pwm1m1-ch0 {
+ rockchip,pins =
+ /* pwm1m1_ch0 */
+ <2 RK_PA3 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm1m1_ch1: pwm1m1-ch1 {
+ rockchip,pins =
+ /* pwm1m1_ch1 */
+ <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm1m1_ch2: pwm1m1-ch2 {
+ rockchip,pins =
+ /* pwm1m1_ch2 */
+ <2 RK_PA5 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm1m1_ch3: pwm1m1-ch3 {
+ rockchip,pins =
+ /* pwm1m1_ch3 */
+ <2 RK_PB1 3 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_ch0: pwm2m0-ch0 {
+ rockchip,pins =
+ /* pwm2m0_ch0 */
+ <1 RK_PB0 4 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm2m0_ch1: pwm2m0-ch1 {
+ rockchip,pins =
+ /* pwm2m0_ch1 */
+ <1 RK_PA7 4 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm2m0_ch2: pwm2m0-ch2 {
+ rockchip,pins =
+ /* pwm2m0_ch2 */
+ <1 RK_PB4 4 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm2m0_ch3: pwm2m0-ch3 {
+ rockchip,pins =
+ /* pwm2m0_ch3 */
+ <1 RK_PB3 4 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch0: pwm2m1-ch0 {
+ rockchip,pins =
+ /* pwm2m1_ch0 */
+ <2 RK_PA6 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm2m1_ch1: pwm2m1-ch1 {
+ rockchip,pins =
+ /* pwm2m1_ch1 */
+ <2 RK_PA7 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm2m1_ch2: pwm2m1-ch2 {
+ rockchip,pins =
+ /* pwm2m1_ch2 */
+ <2 RK_PB2 3 &pcfg_pull_none_drv_level_0>;
+ };
+ /omit-if-no-ref/
+ pwm2m1_ch3: pwm2m1-ch3 {
+ rockchip,pins =
+ /* pwm2m1_ch3 */
+ <2 RK_PB3 3 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwr {
+ /omit-if-no-ref/
+ pwr: pwr {
+ rockchip,pins =
+ /* pwr_ctrl0 */
+ <0 RK_PA3 1 &pcfg_pull_none>,
+ /* pwr_ctrl1 */
+ <0 RK_PA4 1 &pcfg_pull_none>;
+ };
+ };
+
+ rtc_32k {
+ /omit-if-no-ref/
+ rtc_32k: rtc-32k {
+ rockchip,pins =
+ /* rtc_32k_out */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ sai {
+ /omit-if-no-ref/
+ sai: sai {
+ rockchip,pins =
+ /* sai_lrck */
+ <2 RK_PB1 5 &pcfg_pull_none>,
+ /* sai_mclk */
+ <2 RK_PB0 5 &pcfg_pull_none>,
+ /* sai_sclk */
+ <2 RK_PA7 5 &pcfg_pull_none>,
+ /* sai_sdi */
+ <2 RK_PA6 5 &pcfg_pull_none>,
+ /* sai_sdo */
+ <2 RK_PB2 5 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ /* sdmmc0_det */
+ <1 RK_PA6 1 &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_clk: spi0m0-clk {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <2 RK_PB0 2 &pcfg_pull_none>,
+ /* spi0_miso_m0 */
+ <2 RK_PB3 2 &pcfg_pull_none>,
+ /* spi0_mosi_m0 */
+ <2 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0n_m0 */
+ <2 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1n_m0 */
+ <2 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_clk: spi0m1-clk {
+ rockchip,pins =
+ /* spi0_clk_m1 */
+ <2 RK_PA2 5 &pcfg_pull_none>,
+ /* spi0_miso_m1 */
+ <2 RK_PA4 5 &pcfg_pull_none>,
+ /* spi0_mosi_m1 */
+ <2 RK_PA1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0n_m1 */
+ <2 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs1: spi0m1-cs1 {
+ rockchip,pins =
+ /* spi0_cs1n_m1 */
+ <2 RK_PA0 5 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PA6 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PA5 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <0 RK_PB5 2 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <0 RK_PB4 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m2_xfer: uart0m2-xfer {
+ rockchip,pins =
+ /* uart0_rx_m2 */
+ <1 RK_PB3 2 &pcfg_pull_up>,
+ /* uart0_tx_m2 */
+ <1 RK_PB4 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB2 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB3 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <0 RK_PB5 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <0 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <1 RK_PA7 2 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <1 RK_PB0 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <1 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_xfer: uart1m2-xfer {
+ rockchip,pins =
+ /* uart1_rx_m2 */
+ <2 RK_PA7 1 &pcfg_pull_up>,
+ /* uart1_tx_m2 */
+ <2 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_ctsn: uart1m2-ctsn {
+ rockchip,pins =
+ /* uart1m2_ctsn */
+ <2 RK_PA5 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m2_rtsn: uart1m2-rtsn {
+ rockchip,pins =
+ /* uart1m2_rtsn */
+ <2 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m3_xfer: uart1m3-xfer {
+ rockchip,pins =
+ /* uart1_rx_m3 */
+ <2 RK_PA3 2 &pcfg_pull_up>,
+ /* uart1_tx_m3 */
+ <2 RK_PA2 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m3_ctsn: uart1m3-ctsn {
+ rockchip,pins =
+ /* uart1m3_ctsn */
+ <2 RK_PA1 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m3_rtsn: uart1m3-rtsn {
+ rockchip,pins =
+ /* uart1m3_rtsn */
+ <2 RK_PA0 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PB1 2 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PB0 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <0 RK_PB3 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <0 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <2 RK_PB1 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <2 RK_PB0 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <2 RK_PB3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <2 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_xfer: uart2m2-xfer {
+ rockchip,pins =
+ /* uart2_rx_m2 */
+ <1 RK_PB6 3 &pcfg_pull_up>,
+ /* uart2_tx_m2 */
+ <1 RK_PB5 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_ctsn: uart2m2-ctsn {
+ rockchip,pins =
+ /* uart2m2_ctsn */
+ <1 RK_PC0 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m2_rtsn: uart2m2-rtsn {
+ rockchip,pins =
+ /* uart2m2_rtsn */
+ <1 RK_PB7 3 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rockchip/rv1103b.dtsi b/arch/arm/boot/dts/rockchip/rv1103b.dtsi
new file mode 100644
index 000000000000..5955b249d4ce
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b.dtsi
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1103b";
+
+ interrupt-parent = <&gic>;
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ xin32k: oscillator-32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ xin24m: oscillator-24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1103b-pinctrl";
+ rockchip,grf = <&ioc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio@20520000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20520000 0x200>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@20d80000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20d80000 0x200>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@20840000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20840000 0x200>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rv1103b-cru";
+ reg = <0x20000000 0x81000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ pmu_grf: syscon@20160000 {
+ compatible = "rockchip,rv1103b-pmu-grf", "syscon", "simple-mfd";
+ reg = <0x20160000 0x1000>;
+
+ reboot_mode: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
+ };
+
+ ioc: syscon@20170000 {
+ compatible = "rockchip,rv1103b-ioc", "syscon";
+ reg = <0x20170000 0x60000>;
+ };
+
+ gic: interrupt-controller@20411000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x20411000 0x1000>,
+ <0x20412000 0x2000>,
+ <0x20414000 0x2000>,
+ <0x20416000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ uart0: serial@20540000 {
+ compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
+ reg = <0x20540000 0x100>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@20650000 {
+ compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x20650000 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ status = "disabled";
+ };
+
+ uart1: serial@20870000 {
+ compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
+ reg = <0x20870000 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ status = "disabled";
+ };
+
+ uart2: serial@20880000 {
+ compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
+ reg = <0x20880000 0x100>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@208d0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x208d0000 0x100>;
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sdmmc0: mmc@20d20000 {
+ compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x20d20000 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_det &sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>;
+ status = "disabled";
+ };
+
+ emmc: mmc@20d30000 {
+ compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x20d30000 0x4000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
+ status = "disabled";
+ };
+
+ fspi0: spi@20d40000 {
+ compatible = "rockchip,sfc";
+ reg = <0x20d40000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_bus4 &fspi_cs0 &fspi_clk>;
+ status = "disabled";
+ };
+
+ system_sram: sram@210f6000 {
+ compatible = "mmio-sram";
+ reg = <0x210f6000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x210f6000 0x8000>;
+ };
+ };
+};
+
+#include "rv1103b-pinctrl.dtsi"
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v4 3/4] dt-bindings: arm: rockchip: Add Omega4 Evaluation board
2026-02-11 11:05 [PATCH v4 1/4] dt-bindings: soc: rockchip: grf: Add RV1103B compatibles Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 2/4] ARM: dts: rockchip: Add support for RV1103B Fabio Estevam
@ 2026-02-11 11:05 ` Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 4/4] ARM: dts: rockchip: Add Onion Omega4 Evaluation Board Fabio Estevam
2 siblings, 0 replies; 4+ messages in thread
From: Fabio Estevam @ 2026-02-11 11:05 UTC (permalink / raw)
To: heiko
Cc: jonas, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
The Onion Omega4 Evaluation Board is based on the Omega4 SoM.
Document its compatibles.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
Changes since v3:
- Split into SoM and base board.
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index d496421dbd87..8e8f9ded2484 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -802,6 +802,12 @@ properties:
- const: netxeon,r89
- const: rockchip,rk3288
+ - description: Onion Omega4 Evaluation board
+ items:
+ - const: onion,rv1103b-omega4-evb
+ - const: onion,rv1103b-omega4
+ - const: rockchip,rv1103b
+
- description: OPEN AI LAB EAIDK-610
items:
- const: openailab,eaidk-610
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v4 4/4] ARM: dts: rockchip: Add Onion Omega4 Evaluation Board
2026-02-11 11:05 [PATCH v4 1/4] dt-bindings: soc: rockchip: grf: Add RV1103B compatibles Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 2/4] ARM: dts: rockchip: Add support for RV1103B Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 3/4] dt-bindings: arm: rockchip: Add Omega4 Evaluation board Fabio Estevam
@ 2026-02-11 11:05 ` Fabio Estevam
2 siblings, 0 replies; 4+ messages in thread
From: Fabio Estevam @ 2026-02-11 11:05 UTC (permalink / raw)
To: heiko
Cc: jonas, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
The Onion Omega4 Evaluation Board is based on the Omega4 SoM and has:
- 256 MB of RAM
- 256 MB of SPI-NAND
- Ethernet
- USB OTG
- Wifi
- SD card
- Camera connector
The details can be found at:
https://documentation.onioniot.com/omega4/getting-started/
Add the initial support for this board so that it can fully boot into
Linux with the root file system stored in the SPI NAND.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
Changes since v3:
- Split into SoM and base board.
arch/arm/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rv1103b-omega4-evb.dts | 55 ++++++++++++++++
.../arm/boot/dts/rockchip/rv1103b-omega4.dtsi | 65 +++++++++++++++++++
3 files changed, 121 insertions(+)
create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts
create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi
diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index 716f5540e438..d0154fd7ff24 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rv1103b-omega4-evb.dtb \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
rv1109-relfor-saib.dtb \
diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts
new file mode 100644
index 000000000000..c42e99841be4
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2025 plan44.ch/luz
+ * Copyright (c) 2025 Onion Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "rv1103b-omega4.dtsi"
+
+/ {
+ model = "Onion Omega4 Evaluation Board";
+ compatible = "onion,rv1103b-omega4-evb", "onion,rv1103b-omega4", "rockchip,rv1103b";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&led>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "sys";
+ default-state = "on";
+ };
+ };
+};
+
+&fspi0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ led: led {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi
new file mode 100644
index 000000000000..58aebffda9cd
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2025 plan44.ch/luz
+ * Copyright (c) 2025 Onion Corporation
+ */
+
+/dts-v1/;
+
+#include "rv1103b.dtsi"
+
+&uart0 {
+ bootph-all;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+};
+
+&fspi0 {
+ spi_nand: flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <75000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "env";
+ reg = <0x00000000 0x00040000>;
+ };
+
+ partition@40000 {
+ label = "idblock";
+ reg = <0x00040000 0x00100000>;
+ read-only;
+ };
+
+ partition@140000 {
+ label = "uboot";
+ reg = <0x00140000 0x00100000>;
+ read-only;
+ };
+
+ partition@240000 {
+ label = "boot";
+ reg = <0x00240000 0x00800000>;
+ };
+
+ partition@a40000 {
+ label = "ubi";
+ reg = <0x00a40000 0x0f5c0000>;
+ };
+ };
+ };
+};
+
+&wdt {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2026-02-11 11:05 [PATCH v4 1/4] dt-bindings: soc: rockchip: grf: Add RV1103B compatibles Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 2/4] ARM: dts: rockchip: Add support for RV1103B Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 3/4] dt-bindings: arm: rockchip: Add Omega4 Evaluation board Fabio Estevam
2026-02-11 11:05 ` [PATCH v4 4/4] ARM: dts: rockchip: Add Onion Omega4 Evaluation Board Fabio Estevam
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