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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4835d989165sm54303495e9.2.2026.02.11.05.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 05:43:43 -0800 (PST) Date: Wed, 11 Feb 2026 13:43:42 +0000 From: David Laight To: Andrew Cooper Cc: ubizjak@gmail.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, mingo@kernel.org, pbonzini@redhat.com, seanjc@google.com, tglx@kernel.org, x86@kernel.org Subject: Re: [PATCH 1/2] KVM: VMX: Drop obsolete branch hint prefixes from inline asm Message-ID: <20260211134342.45b7e19e@pumpkin> In-Reply-To: <2af5e3a8-f520-40fd-96a5-28555c3e4a5e@citrix.com> References: <20260211102928.100944-1-ubizjak@gmail.com> <2af5e3a8-f520-40fd-96a5-28555c3e4a5e@citrix.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 11 Feb 2026 10:57:31 +0000 Andrew Cooper wrote: > > Remove explicit branch hint prefixes (.byte 0x2e / 0x3e) from VMX > > inline assembly sequences. > > > > These prefixes (CS/DS segment overrides used as branch hints on > > very old x86 CPUs) have been ignored by modern processors for a > > long time. Keeping them provides no measurable benefit and only > > enlarges the generated code. > > It's actually worse than this. > > The branch-taken hint has new meaning in Lion Cove cores and later, > along with a warning saying "performance penalty for misuse". > > i.e. "only insert this prefix after profiling". Don't they really have much the same meaning as before? Perhaps the branch prediction logic is ignored (which would make getting then wrong very bad). But here (and a few other places) the branch really is 'never taken', so perhaps the branch hints should have been removed 20 years ago and now is the time to add them back? Of course, the branch-hint can only have an effect when the branch prediction logic gets to see the branch. The initial instruction prefetch (etc) is done without regard to the contents of the memory being read - so initially all branches are effectively predicted 'not-taken'. (I got the impression that some AMD cpu 'attached' some of the branch prediction info to the cache-line - and would use it when the cache line was re-used for an entirely different address. Hence the issues where non-branch instructions would be predicted as branches.) David > > ~Andrew >