From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from MTA-15-3.privateemail.com (MTA-15-3.privateemail.com [198.54.122.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 270551F4613 for ; Thu, 12 Feb 2026 23:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.54.122.111 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770937820; cv=none; b=PfrH7+u4flkltwCekpvw0zRHdPkCJqYofYX40GbEPyDMu3ylpJpv1e2UtxZeu+AsEmqjyvWQ1BYJhds4MNRIhFOC72LDSEb+godIB88YeYwPfMEvFtWRG1osoBEQEtRS5rxkFlLHpqA+8CT3MxG8u7v3IrYh0ttbL5PHGsQyO2M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770937820; c=relaxed/simple; bh=sEiW2MVKueZys4xZnfrg4/0n11/oQg1QrC6QsU8liUI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JwNSwkyCTc3WDw2x3Si7x/cpF/YPY2Ol82jviwtwR8sUSFErl+1fq4X5j5d+8iLEUjk7OfK0jWtrdnf8yLYvan2t+jDmEudKmWn9/XXPzpLYXy/ZNYgJrJIjJ+Vpf2isv8xmVX+NbOUaoHiUKoRpelsb1HcGN9p+QLiuB8VYSqM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=effective-light.com; spf=pass smtp.mailfrom=effective-light.com; arc=none smtp.client-ip=198.54.122.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=effective-light.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=effective-light.com Received: from mta-15.privateemail.com (localhost [127.0.0.1]) by mta-15.privateemail.com (Postfix) with ESMTP id 4fBrcV0y0Lz3hhSx; Thu, 12 Feb 2026 18:10:18 -0500 (EST) Received: from localhost.localdomain (bras-base-toroon4332w-grc-26-174-91-51-28.dsl.bell.ca [174.91.51.28]) by mta-15.privateemail.com (Postfix) with ESMTPA; Thu, 12 Feb 2026 18:09:50 -0500 (EST) From: Hamza Mahfooz To: dri-devel@lists.freedesktop.org Cc: =?UTF-8?q?Michel=20D=C3=A4nzer?= , Hamza Mahfooz , Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Mario Limonciello , Alex Hung , Aurabindo Pillai , Wayne Lin , Ivan Lipski , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Dominik Kaszewski , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] drm/amd/display: add vendor specific reset Date: Thu, 12 Feb 2026 18:09:00 -0500 Message-ID: <20260212230905.688006-2-someguy@effective-light.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260212230905.688006-1-someguy@effective-light.com> References: <20260212230905.688006-1-someguy@effective-light.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Virus-Scanned: ClamAV using ClamSMTP We now have a means to respond to page flip timeouts. So, hook up support by sending out a wedged event if drm_atomic_helper_wait_for_flip_done() fails. Signed-off-by: Hamza Mahfooz --- v2: send a wedged event instead of attempting a GPU reset. v3: read return value of drm_atomic_helper_wait_for_flip_done(). --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7c51d8d7e73c..06d8353cb616 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -87,6 +87,7 @@ #include #include #include +#include #include #include #include @@ -11085,8 +11086,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Signal HW programming completion */ drm_atomic_helper_commit_hw_done(state); - if (wait_for_vblank) - drm_atomic_helper_wait_for_flip_done(dev, state); + if (wait_for_vblank) { + if (drm_atomic_helper_wait_for_flip_done(dev, state)) + drm_dev_wedged_event(dev, DRM_WEDGE_RECOVERY_REBIND | + DRM_WEDGE_RECOVERY_BUS_RESET, + NULL); + } drm_atomic_helper_cleanup_planes(dev, state); -- 2.53.0