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From: "Ionut Nechita (Sunlight Linux)" <sunlightlinux@gmail.com>
To: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>
Cc: Zhang Rui <rui.zhang@intel.com>,
	Lukasz Luba <lukasz.luba@arm.com>, Lukas Wunner <lukas@wunner.de>,
	Ionut Nechita <sunlightlinux@gmail.com>,
	linux-pci@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Ionut Nechita <ionut_n2001@yahoo.com>
Subject: [RFC PATCH 0/3] PCI: Add PCIe Gen 7 (128 GT/s) speed support
Date: Tue, 17 Feb 2026 10:00:56 +0200	[thread overview]
Message-ID: <20260217080102.206581-2-sunlightlinux@gmail.com> (raw)

From: Ionut Nechita <ionut_n2001@yahoo.com>

This RFC series adds initial kernel support for PCIe Gen 7 128 GT/s
link speed, following the same pattern used for Gen 6 (64 GT/s).

PCIe Gen 7 doubles the per-lane data rate to 128 GT/s using PAM4
signaling with mandatory Flit mode encoding (1:1, no overhead),
providing up to 256 GB/s unidirectional (512 GB/s bi-directional)
bandwidth on an x16 link. The specification was announced by PCI-SIG
in 2022 and targeted for member release in 2025.

The series covers:

  Patch 1: UAPI register definitions (LNKCAP, LNKCAP2, LNKCTL2) and
           pci_bus_speed enum. Widens supported_speeds from u8 to u16
           to accommodate the expanded Supported Link Speeds Vector.

  Patch 2: Core PCI infrastructure - speed detection macros, bandwidth
           calculation with 1:1 Flit mode encoding, link speed table,
           display string, and a pcie_speed_requires_flit() helper
           with Flit mode diagnostic warning for Gen 6+ speeds.

  Patch 3: Subsystem updates for bandwidth control (bwctrl), port
           driver, and PCIe thermal cooling.

Not included in this series (not yet defined in the specification):
  - Equalization presets for 128 GT/s (PCI_EXT_CAP_ID_PL_128GT)
  - DesignWare controller preset programming for Gen 7

This is marked as RFC since no PCIe Gen 7 hardware exists yet to
validate the implementation. The register encoding values (LNKCAP
SLS=0x7, LNKCAP2 SLS bit 6, LNKCTL2 TLS=0x7) follow the sequential
pattern established by prior generations and are subject to change
when the final specification is published.

Tested: compile-tested only (no hardware available).

Ionut Nechita (3):
  PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions
  PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting
  PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s)

 drivers/pci/pci.c              |  7 +++++--
 drivers/pci/pci.h              | 28 ++++++++++++++++++++++------
 drivers/pci/pcie/bwctrl.c      |  7 ++++---
 drivers/pci/pcie/portdrv.c     |  2 +-
 drivers/pci/probe.c            |  3 ++-
 drivers/thermal/pcie_cooling.c |  1 +
 include/linux/pci.h            |  3 ++-
 include/uapi/linux/pci_regs.h  |  3 +++
 8 files changed, 40 insertions(+), 14 deletions(-)

-- 
2.53.0


             reply	other threads:[~2026-02-17  8:01 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-17  8:00 Ionut Nechita (Sunlight Linux) [this message]
2026-02-17  8:00 ` [RFC PATCH 1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions Ionut Nechita (Sunlight Linux)
2026-02-18 20:26   ` Ilpo Järvinen
2026-02-17  8:01 ` [RFC PATCH 2/3] PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting Ionut Nechita (Sunlight Linux)
2026-02-18 21:05   ` Ilpo Järvinen
2026-02-17  8:01 ` [RFC PATCH 3/3] PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s) Ionut Nechita (Sunlight Linux)
2026-02-18 21:08   ` Ilpo Järvinen

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