[RFC PATCH 0/3] PCI: Add PCIe Gen 7 (128 GT/s) speed support

[RFC PATCH 0/3] PCI: Add PCIe Gen 7 (128 GT/s) speed support

[Ionut Nechita (Sunlight Linux)]

From: Ionut Nechita <ionut_n2001@yahoo.com>

This RFC series adds initial kernel support for PCIe Gen 7 128 GT/s
link speed, following the same pattern used for Gen 6 (64 GT/s).

PCIe Gen 7 doubles the per-lane data rate to 128 GT/s using PAM4
signaling with mandatory Flit mode encoding (1:1, no overhead),
providing up to 256 GB/s unidirectional (512 GB/s bi-directional)
bandwidth on an x16 link. The specification was announced by PCI-SIG
in 2022 and targeted for member release in 2025.

The series covers:

  Patch 1: UAPI register definitions (LNKCAP, LNKCAP2, LNKCTL2) and
           pci_bus_speed enum. Widens supported_speeds from u8 to u16
           to accommodate the expanded Supported Link Speeds Vector.

  Patch 2: Core PCI infrastructure - speed detection macros, bandwidth
           calculation with 1:1 Flit mode encoding, link speed table,
           display string, and a pcie_speed_requires_flit() helper
           with Flit mode diagnostic warning for Gen 6+ speeds.

  Patch 3: Subsystem updates for bandwidth control (bwctrl), port
           driver, and PCIe thermal cooling.

Not included in this series (not yet defined in the specification):
  - Equalization presets for 128 GT/s (PCI_EXT_CAP_ID_PL_128GT)
  - DesignWare controller preset programming for Gen 7

This is marked as RFC since no PCIe Gen 7 hardware exists yet to
validate the implementation. The register encoding values (LNKCAP
SLS=0x7, LNKCAP2 SLS bit 6, LNKCTL2 TLS=0x7) follow the sequential
pattern established by prior generations and are subject to change
when the final specification is published.

Tested: compile-tested only (no hardware available).

Ionut Nechita (3):
  PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions
  PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting
  PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s)

 drivers/pci/pci.c              |  7 +++++--
 drivers/pci/pci.h              | 28 ++++++++++++++++++++++------
 drivers/pci/pcie/bwctrl.c      |  7 ++++---
 drivers/pci/pcie/portdrv.c     |  2 +-
 drivers/pci/probe.c            |  3 ++-
 drivers/thermal/pcie_cooling.c |  1 +
 include/linux/pci.h            |  3 ++-
 include/uapi/linux/pci_regs.h  |  3 +++
 8 files changed, 40 insertions(+), 14 deletions(-)

-- 
2.53.0

[RFC PATCH 1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions

[Ionut Nechita (Sunlight Linux)]

From: Ionut Nechita <ionut_n2001@yahoo.com>

Add register definitions for PCIe Gen 7 128 GT/s link speed:

  - PCI_EXP_LNKCAP_SLS_128_0GB (encoding 0x7)
  - PCI_EXP_LNKCAP2_SLS_128_0GB (bit 6 in Supported Link Speeds Vector)
  - PCI_EXP_LNKCTL2_TLS_128_0GT (Target Link Speed 0x7)
  - PCIE_SPEED_128_0GT enum value (0x1a)

Widen pci_dev.supported_speeds from u8 to u16 to accommodate the
expanded Supported Link Speeds Vector which now uses bits 1-7.

PCIe Gen 7 doubles the data rate to 128 GT/s using PAM4 signaling
with mandatory Flit mode encoding (1:1, no overhead), providing
up to 256 GB/s unidirectional (512 GB/s bi-directional) bandwidth
on an x16 link.

Note: Based on the PCIe 7.0 specification announced by PCI-SIG in
2022, targeted for member release in 2025. No hardware exists yet
to validate these definitions.

Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
---
 include/linux/pci.h           | 3 ++-
 include/uapi/linux/pci_regs.h | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/linux/pci.h b/include/linux/pci.h
index b5cc0c2b99065..21dd6ea5beb6d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -303,6 +303,7 @@ enum pci_bus_speed {
 	PCIE_SPEED_16_0GT		= 0x17,
 	PCIE_SPEED_32_0GT		= 0x18,
 	PCIE_SPEED_64_0GT		= 0x19,
+	PCIE_SPEED_128_0GT		= 0x1a,
 	PCI_SPEED_UNKNOWN		= 0xff,
 };
 
@@ -558,7 +559,7 @@ struct pci_dev {
 	struct pci_tsm *tsm;		/* TSM operation state */
 #endif
 	u16		acs_cap;	/* ACS Capability offset */
-	u8		supported_speeds; /* Supported Link Speeds Vector */
+	u16		supported_speeds; /* Supported Link Speeds Vector */
 	phys_addr_t	rom;		/* Physical address if not from BAR */
 	size_t		romlen;		/* Length if not from BAR */
 	/*
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 3add74ae25948..fa00c6ca9f382 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -545,6 +545,7 @@
 #define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
 #define  PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
 #define  PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
+#define  PCI_EXP_LNKCAP_SLS_128_0GB 0x00000007 /* LNKCAP2 SLS Vector bit 6 */
 #define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
@@ -693,6 +694,7 @@
 #define  PCI_EXP_LNKCAP2_SLS_16_0GB	0x00000010 /* Supported Speed 16GT/s */
 #define  PCI_EXP_LNKCAP2_SLS_32_0GB	0x00000020 /* Supported Speed 32GT/s */
 #define  PCI_EXP_LNKCAP2_SLS_64_0GB	0x00000040 /* Supported Speed 64GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_128_0GB	0x00000080 /* Supported Speed 128GT/s */
 #define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2		0x30	/* Link Control 2 */
 #define  PCI_EXP_LNKCTL2_TLS		0x000f
@@ -702,6 +704,7 @@
 #define  PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */
 #define  PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005 /* Supported Speed 32GT/s */
 #define  PCI_EXP_LNKCTL2_TLS_64_0GT	0x0006 /* Supported Speed 64GT/s */
+#define  PCI_EXP_LNKCTL2_TLS_128_0GT	0x0007 /* Supported Speed 128GT/s */
 #define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
 #define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
 #define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */
-- 
2.53.0

[RFC PATCH 2/3] PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting

[Ionut Nechita (Sunlight Linux)]

From: Ionut Nechita <ionut_n2001@yahoo.com>

Add kernel infrastructure to detect and report PCIe Gen 7 128 GT/s
link speeds:

  - Extend PCIE_LNKCAP_SLS2SPEED, PCIE_LNKCAP2_SLS2SPEED, and
    PCIE_LNKCTL2_TLS2SPEED macros with 128 GT/s mapping
  - Add 128 GT/s to PCIE_SPEED2MBS_ENC bandwidth calculation using
    1:1 Flit mode encoding (no overhead), consistent with Gen 6
  - Add PCIE_SPEED_128_0GT to pcie_dev_speed_mbps() switch
  - Map link speed encoding 7 to PCIE_SPEED_128_0GT in
    pcie_link_speed[] table
  - Add "128.0 GT/s PCIe" display string
  - Add pcie_speed_requires_flit() helper for Gen 6+ speed
    validation with proper range check against PCI_SPEED_UNKNOWN
  - Widen pcie_get_supported_speeds() return type from u8 to u16
  - Add Flit mode diagnostic warning when Gen 6+ speed is active
    but PCI_EXP_LNKSTA2_FLIT is not set

Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
---
 drivers/pci/pci.c   |  7 +++++--
 drivers/pci/pci.h   | 28 ++++++++++++++++++++++------
 drivers/pci/probe.c |  3 ++-
 3 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 13dbb405dc31f..8091f7bf30e6f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5912,10 +5912,10 @@ EXPORT_SYMBOL(pcie_bandwidth_available);
  *
  * Return: Supported Link Speeds Vector (+ reserved 0 at LSB).
  */
-u8 pcie_get_supported_speeds(struct pci_dev *dev)
+u16 pcie_get_supported_speeds(struct pci_dev *dev)
 {
 	u32 lnkcap2, lnkcap;
-	u8 speeds;
+	u16 speeds;
 
 	/*
 	 * Speeds retain the reserved 0 at LSB before PCIe Supported Link
@@ -6020,6 +6020,9 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
 
 	if (dev->bus && dev->bus->flit_mode)
 		flit_mode = ", in Flit mode";
+	else if (dev->bus && pcie_speed_requires_flit(dev->bus->cur_bus_speed))
+		pci_warn(dev, "Flit mode not active at %s, expected for Gen 6+\n",
+			 pci_speed_string(dev->bus->cur_bus_speed));
 
 	if (bw_avail >= bw_cap && verbose)
 		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)%s\n",
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 60542b05de0c6..4dd23f0d5de9f 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -487,7 +487,8 @@ void pci_bus_put(struct pci_bus *bus);
 ({									\
 	u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS;			\
 									\
-	(lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :	\
+	(lnkcap_sls == PCI_EXP_LNKCAP_SLS_128_0GB ? PCIE_SPEED_128_0GT :	\
+	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :	\
 	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT :	\
 	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT :	\
 	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT :	\
@@ -498,7 +499,8 @@ void pci_bus_put(struct pci_bus *bus);
 
 /* PCIe link information from Link Capabilities 2 */
 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
-	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
+	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_128_0GB ? PCIE_SPEED_128_0GT : \
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
 	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
 	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
 	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
@@ -510,7 +512,8 @@ void pci_bus_put(struct pci_bus *bus);
 ({									\
 	u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS;		\
 									\
-	(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :	\
+	(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_128_0GT ? PCIE_SPEED_128_0GT :	\
+	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :	\
 	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT :	\
 	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT :	\
 	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT :	\
@@ -519,9 +522,14 @@ void pci_bus_put(struct pci_bus *bus);
 	 PCI_SPEED_UNKNOWN);						\
 })
 
-/* PCIe speed to Mb/s reduced by encoding overhead */
+/* PCIe speed to Mb/s reduced by encoding overhead:
+ *   Gen 1-2 (2.5, 5 GT/s):       8b/10b encoding
+ *   Gen 3-5 (8, 16, 32 GT/s):    128b/130b encoding
+ *   Gen 6+  (64, 128 GT/s):      Flit mode, 1:1 (no encoding overhead)
+ */
 #define PCIE_SPEED2MBS_ENC(speed) \
-	((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
+	((speed) == PCIE_SPEED_128_0GT ? 128000*1/1 : \
+	 (speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
 	 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
 	 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 	 (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
@@ -544,6 +552,8 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
 		return 32000;
 	case PCIE_SPEED_64_0GT:
 		return 64000;
+	case PCIE_SPEED_128_0GT:
+		return 128000;
 	default:
 		break;
 	}
@@ -551,7 +561,13 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
 	return -EINVAL;
 }
 
-u8 pcie_get_supported_speeds(struct pci_dev *dev);
+/* PCIe Gen 6+ (>= 64 GT/s) requires Flit mode with 1:1 encoding */
+static inline bool pcie_speed_requires_flit(enum pci_bus_speed speed)
+{
+	return speed >= PCIE_SPEED_64_0GT && speed <= PCIE_SPEED_128_0GT;
+}
+
+u16 pcie_get_supported_speeds(struct pci_dev *dev);
 const char *pci_speed_string(enum pci_bus_speed speed);
 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 void pcie_report_downtraining(struct pci_dev *dev);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 9d4eeda5ea946..031c3ec8615d2 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -774,7 +774,7 @@ const unsigned char pcie_link_speed[] = {
 	PCIE_SPEED_16_0GT,		/* 4 */
 	PCIE_SPEED_32_0GT,		/* 5 */
 	PCIE_SPEED_64_0GT,		/* 6 */
-	PCI_SPEED_UNKNOWN,		/* 7 */
+	PCIE_SPEED_128_0GT,		/* 7 */
 	PCI_SPEED_UNKNOWN,		/* 8 */
 	PCI_SPEED_UNKNOWN,		/* 9 */
 	PCI_SPEED_UNKNOWN,		/* A */
@@ -816,6 +816,7 @@ const char *pci_speed_string(enum pci_bus_speed speed)
 	    "16.0 GT/s PCIe",		/* 0x17 */
 	    "32.0 GT/s PCIe",		/* 0x18 */
 	    "64.0 GT/s PCIe",		/* 0x19 */
+	    "128.0 GT/s PCIe",		/* 0x1a */
 	};
 
 	if (speed < ARRAY_SIZE(speed_strings))
-- 
2.53.0

[RFC PATCH 3/3] PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s)

[Ionut Nechita (Sunlight Linux)]

From: Ionut Nechita <ionut_n2001@yahoo.com>

Update PCIe subsystem components to support 128 GT/s link speed:

  - bwctrl: Extend pcie_valid_speed() range to PCIE_SPEED_128_0GT,
    add PCIE_SPEED_128_0GT to speed conversion table, widen
    supported_speeds variables from u8 to u16
  - portdrv: Switch hweight8() to hweight16() for supported_speeds
    to match the widened type
  - pcie_cooling: Add static_assert for PCIE_SPEED_128_0GT enum
    contiguity check

Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
---
 drivers/pci/pcie/bwctrl.c      | 7 ++++---
 drivers/pci/pcie/portdrv.c     | 2 +-
 drivers/thermal/pcie_cooling.c | 1 +
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
index 36f939f23d34e..b9125b40cb860 100644
--- a/drivers/pci/pcie/bwctrl.c
+++ b/drivers/pci/pcie/bwctrl.c
@@ -50,7 +50,7 @@ static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
 
 static bool pcie_valid_speed(enum pci_bus_speed speed)
 {
-	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
+	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_128_0GT);
 }
 
 static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
@@ -62,6 +62,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
 		[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
 		[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
 		[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
+		[PCIE_SPEED_128_0GT] = PCI_EXP_LNKCTL2_TLS_128_0GT,
 	};
 
 	if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
@@ -70,7 +71,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
 	return speed_conv[speed];
 }
 
-static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
+static inline u16 pcie_supported_speeds2target_speed(u16 supported_speeds)
 {
 	return __fls(supported_speeds);
 }
@@ -88,7 +89,7 @@ static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
 static u16 pcie_bwctrl_select_speed(struct pci_dev *port, enum pci_bus_speed speed_req)
 {
 	struct pci_bus *bus = port->subordinate;
-	u8 desired_speeds, supported_speeds;
+	u16 desired_speeds, supported_speeds;
 	struct pci_dev *dev;
 
 	desired_speeds = GENMASK(pci_bus_speed2lnkctl2(speed_req),
diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
index 38a41ccf79b9a..5ee8795107f26 100644
--- a/drivers/pci/pcie/portdrv.c
+++ b/drivers/pci/pcie/portdrv.c
@@ -274,7 +274,7 @@ static int get_port_device_capability(struct pci_dev *dev)
 
 		pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap);
 		if (linkcap & PCI_EXP_LNKCAP_LBNC &&
-		    hweight8(dev->supported_speeds) > 1)
+		    hweight16(dev->supported_speeds) > 1)
 			services |= PCIE_PORT_SERVICE_BWCTRL;
 	}
 
diff --git a/drivers/thermal/pcie_cooling.c b/drivers/thermal/pcie_cooling.c
index a876d64f15827..9a2e39398674b 100644
--- a/drivers/thermal/pcie_cooling.c
+++ b/drivers/thermal/pcie_cooling.c
@@ -75,6 +75,7 @@ static_assert(PCIE_SPEED_5_0GT + 1 == PCIE_SPEED_8_0GT);
 static_assert(PCIE_SPEED_8_0GT + 1 == PCIE_SPEED_16_0GT);
 static_assert(PCIE_SPEED_16_0GT + 1 == PCIE_SPEED_32_0GT);
 static_assert(PCIE_SPEED_32_0GT + 1 == PCIE_SPEED_64_0GT);
+static_assert(PCIE_SPEED_64_0GT + 1 == PCIE_SPEED_128_0GT);
 
 MODULE_AUTHOR("Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>");
 MODULE_DESCRIPTION("PCIe cooling driver");
-- 
2.53.0

Re: [RFC PATCH 1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions

[Ilpo Järvinen]

On Tue, 17 Feb 2026, Ionut Nechita (Sunlight Linux) wrote:

> From: Ionut Nechita <ionut_n2001@yahoo.com>
> 
> Add register definitions for PCIe Gen 7 128 GT/s link speed:
> 
>   - PCI_EXP_LNKCAP_SLS_128_0GB (encoding 0x7)
>   - PCI_EXP_LNKCAP2_SLS_128_0GB (bit 6 in Supported Link Speeds Vector)
>   - PCI_EXP_LNKCTL2_TLS_128_0GT (Target Link Speed 0x7)
>   - PCIE_SPEED_128_0GT enum value (0x1a)
> 
> Widen pci_dev.supported_speeds from u8 to u16 to accommodate the
> expanded Supported Link Speeds Vector which now uses bits 1-7.
> 
> PCIe Gen 7 doubles the data rate to 128 GT/s using PAM4 signaling
> with mandatory Flit mode encoding (1:1, no overhead), providing
> up to 256 GB/s unidirectional (512 GB/s bi-directional) bandwidth
> on an x16 link.
> 
> Note: Based on the PCIe 7.0 specification announced by PCI-SIG in
> 2022, targeted for member release in 2025. No hardware exists yet

2022?

Please provide more precise spec reference(s) with section numbers (as per 
the usual custom).

> to validate these definitions.
> 
> Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
> ---
>  include/linux/pci.h           | 3 ++-
>  include/uapi/linux/pci_regs.h | 3 +++
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index b5cc0c2b99065..21dd6ea5beb6d 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -303,6 +303,7 @@ enum pci_bus_speed {
>  	PCIE_SPEED_16_0GT		= 0x17,
>  	PCIE_SPEED_32_0GT		= 0x18,
>  	PCIE_SPEED_64_0GT		= 0x19,
> +	PCIE_SPEED_128_0GT		= 0x1a,
>  	PCI_SPEED_UNKNOWN		= 0xff,
>  };
>  
> @@ -558,7 +559,7 @@ struct pci_dev {
>  	struct pci_tsm *tsm;		/* TSM operation state */
>  #endif
>  	u16		acs_cap;	/* ACS Capability offset */
> -	u8		supported_speeds; /* Supported Link Speeds Vector */
> +	u16		supported_speeds; /* Supported Link Speeds Vector */
>  	phys_addr_t	rom;		/* Physical address if not from BAR */
>  	size_t		romlen;		/* Length if not from BAR */
>  	/*
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 3add74ae25948..fa00c6ca9f382 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -545,6 +545,7 @@
>  #define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
>  #define  PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
>  #define  PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
> +#define  PCI_EXP_LNKCAP_SLS_128_0GB 0x00000007 /* LNKCAP2 SLS Vector bit 6 */

Eh, did you make this up? This is not at all what is in the PCIe 7.0 spec!

>  #define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
>  #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
>  #define  PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
> @@ -693,6 +694,7 @@
>  #define  PCI_EXP_LNKCAP2_SLS_16_0GB	0x00000010 /* Supported Speed 16GT/s */
>  #define  PCI_EXP_LNKCAP2_SLS_32_0GB	0x00000020 /* Supported Speed 32GT/s */
>  #define  PCI_EXP_LNKCAP2_SLS_64_0GB	0x00000040 /* Supported Speed 64GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_128_0GB	0x00000080 /* Supported Speed 128GT/s */

This is simplifying this too much, the spec says "128 GT/s or higher".

The actual speeds are in the new 128 GT/s Capability and should be 
read from there.

>  #define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */
>  #define PCI_EXP_LNKCTL2		0x30	/* Link Control 2 */
>  #define  PCI_EXP_LNKCTL2_TLS		0x000f
> @@ -702,6 +704,7 @@
>  #define  PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */
>  #define  PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005 /* Supported Speed 32GT/s */
>  #define  PCI_EXP_LNKCTL2_TLS_64_0GT	0x0006 /* Supported Speed 64GT/s */
> +#define  PCI_EXP_LNKCTL2_TLS_128_0GT	0x0007 /* Supported Speed 128GT/s */

This is wrong as well.

This entire change (the whole series) is not going to be as 
straightforward as you assumed.

>  #define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
>  #define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
>  #define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */

-- 
 i.

Re: [RFC PATCH 2/3] PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting

[Ilpo Järvinen]

On Tue, 17 Feb 2026, Ionut Nechita (Sunlight Linux) wrote:

> From: Ionut Nechita <ionut_n2001@yahoo.com>
> 
> Add kernel infrastructure to detect and report PCIe Gen 7 128 GT/s
> link speeds:
> 
>   - Extend PCIE_LNKCAP_SLS2SPEED, PCIE_LNKCAP2_SLS2SPEED, and
>     PCIE_LNKCTL2_TLS2SPEED macros with 128 GT/s mapping
>   - Add 128 GT/s to PCIE_SPEED2MBS_ENC bandwidth calculation using
>     1:1 Flit mode encoding (no overhead), consistent with Gen 6
>   - Add PCIE_SPEED_128_0GT to pcie_dev_speed_mbps() switch
>   - Map link speed encoding 7 to PCIE_SPEED_128_0GT in
>     pcie_link_speed[] table
>   - Add "128.0 GT/s PCIe" display string
>   - Add pcie_speed_requires_flit() helper for Gen 6+ speed
>     validation with proper range check against PCI_SPEED_UNKNOWN
>   - Widen pcie_get_supported_speeds() return type from u8 to u16

These are all visible from the patch and as such seem pretty redundant 
information.

>   - Add Flit mode diagnostic warning when Gen 6+ speed is active
>     but PCI_EXP_LNKSTA2_FLIT is not set
> 
> Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
> ---
>  drivers/pci/pci.c   |  7 +++++--
>  drivers/pci/pci.h   | 28 ++++++++++++++++++++++------
>  drivers/pci/probe.c |  3 ++-
>  3 files changed, 29 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 13dbb405dc31f..8091f7bf30e6f 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5912,10 +5912,10 @@ EXPORT_SYMBOL(pcie_bandwidth_available);
>   *
>   * Return: Supported Link Speeds Vector (+ reserved 0 at LSB).
>   */
> -u8 pcie_get_supported_speeds(struct pci_dev *dev)
> +u16 pcie_get_supported_speeds(struct pci_dev *dev)
>  {
>  	u32 lnkcap2, lnkcap;
> -	u8 speeds;
> +	u16 speeds;
>  
>  	/*
>  	 * Speeds retain the reserved 0 at LSB before PCIe Supported Link
> @@ -6020,6 +6020,9 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
>  
>  	if (dev->bus && dev->bus->flit_mode)
>  		flit_mode = ", in Flit mode";
> +	else if (dev->bus && pcie_speed_requires_flit(dev->bus->cur_bus_speed))
> +		pci_warn(dev, "Flit mode not active at %s, expected for Gen 6+\n",
> +			 pci_speed_string(dev->bus->cur_bus_speed));

This looks entirely unrelated to the new speed, please put it into own 
patch (and justification in the changelog).

>  
>  	if (bw_avail >= bw_cap && verbose)
>  		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)%s\n",
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 60542b05de0c6..4dd23f0d5de9f 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -487,7 +487,8 @@ void pci_bus_put(struct pci_bus *bus);
>  ({									\
>  	u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS;			\
>  									\
> -	(lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :	\
> +	(lnkcap_sls == PCI_EXP_LNKCAP_SLS_128_0GB ? PCIE_SPEED_128_0GT :	\
> +	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :	\
>  	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT :	\
>  	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT :	\
>  	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT :	\
> @@ -498,7 +499,8 @@ void pci_bus_put(struct pci_bus *bus);
>  
>  /* PCIe link information from Link Capabilities 2 */
>  #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
> -	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
> +	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_128_0GB ? PCIE_SPEED_128_0GT : \
> +	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
>  	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
>  	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
>  	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
> @@ -510,7 +512,8 @@ void pci_bus_put(struct pci_bus *bus);
>  ({									\
>  	u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS;		\
>  									\
> -	(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :	\
> +	(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_128_0GT ? PCIE_SPEED_128_0GT :	\
> +	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :	\
>  	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT :	\
>  	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT :	\
>  	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT :	\
> @@ -519,9 +522,14 @@ void pci_bus_put(struct pci_bus *bus);
>  	 PCI_SPEED_UNKNOWN);						\
>  })
>  
> -/* PCIe speed to Mb/s reduced by encoding overhead */
> +/* PCIe speed to Mb/s reduced by encoding overhead:
> + *   Gen 1-2 (2.5, 5 GT/s):       8b/10b encoding
> + *   Gen 3-5 (8, 16, 32 GT/s):    128b/130b encoding
> + *   Gen 6+  (64, 128 GT/s):      Flit mode, 1:1 (no encoding overhead)
> + */
>  #define PCIE_SPEED2MBS_ENC(speed) \
> -	((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
> +	((speed) == PCIE_SPEED_128_0GT ? 128000*1/1 : \
> +	 (speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
>  	 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
>  	 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
>  	 (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
> @@ -544,6 +552,8 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>  		return 32000;
>  	case PCIE_SPEED_64_0GT:
>  		return 64000;
> +	case PCIE_SPEED_128_0GT:
> +		return 128000;
>  	default:
>  		break;
>  	}
> @@ -551,7 +561,13 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>  	return -EINVAL;
>  }
>  
> -u8 pcie_get_supported_speeds(struct pci_dev *dev);
> +/* PCIe Gen 6+ (>= 64 GT/s) requires Flit mode with 1:1 encoding */
> +static inline bool pcie_speed_requires_flit(enum pci_bus_speed speed)
> +{
> +	return speed >= PCIE_SPEED_64_0GT && speed <= PCIE_SPEED_128_0GT;
> +}
> +
> +u16 pcie_get_supported_speeds(struct pci_dev *dev);
>  const char *pci_speed_string(enum pci_bus_speed speed);
>  void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
>  void pcie_report_downtraining(struct pci_dev *dev);
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 9d4eeda5ea946..031c3ec8615d2 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -774,7 +774,7 @@ const unsigned char pcie_link_speed[] = {
>  	PCIE_SPEED_16_0GT,		/* 4 */
>  	PCIE_SPEED_32_0GT,		/* 5 */
>  	PCIE_SPEED_64_0GT,		/* 6 */
> -	PCI_SPEED_UNKNOWN,		/* 7 */
> +	PCIE_SPEED_128_0GT,		/* 7 */
>  	PCI_SPEED_UNKNOWN,		/* 8 */
>  	PCI_SPEED_UNKNOWN,		/* 9 */
>  	PCI_SPEED_UNKNOWN,		/* A */
> @@ -816,6 +816,7 @@ const char *pci_speed_string(enum pci_bus_speed speed)
>  	    "16.0 GT/s PCIe",		/* 0x17 */
>  	    "32.0 GT/s PCIe",		/* 0x18 */
>  	    "64.0 GT/s PCIe",		/* 0x19 */
> +	    "128.0 GT/s PCIe",		/* 0x1a */
>  	};
>  
>  	if (speed < ARRAY_SIZE(speed_strings))
> 

-- 
 i.

Re: [RFC PATCH 3/3] PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s)

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 4097 bytes --]

On Tue, 17 Feb 2026, Ionut Nechita (Sunlight Linux) wrote:

The subject should start with

PCI/bwctrl:

...and you then don't need to repeat bandwidth control anymore.

> From: Ionut Nechita <ionut_n2001@yahoo.com>
> 
> Update PCIe subsystem components to support 128 GT/s link speed:
> 
>   - bwctrl: Extend pcie_valid_speed() range to PCIE_SPEED_128_0GT,
>     add PCIE_SPEED_128_0GT to speed conversion table, widen
>     supported_speeds variables from u8 to u16
>   - portdrv: Switch hweight8() to hweight16() for supported_speeds
>     to match the widened type
>   - pcie_cooling: Add static_assert for PCIE_SPEED_128_0GT enum
>     contiguity check
> 
> Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
> ---
>  drivers/pci/pcie/bwctrl.c      | 7 ++++---
>  drivers/pci/pcie/portdrv.c     | 2 +-
>  drivers/thermal/pcie_cooling.c | 1 +
>  3 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> index 36f939f23d34e..b9125b40cb860 100644
> --- a/drivers/pci/pcie/bwctrl.c
> +++ b/drivers/pci/pcie/bwctrl.c
> @@ -50,7 +50,7 @@ static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>  
>  static bool pcie_valid_speed(enum pci_bus_speed speed)
>  {
> -	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> +	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_128_0GT);
>  }
>  
>  static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> @@ -62,6 +62,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
>  		[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
>  		[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
>  		[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
> +		[PCIE_SPEED_128_0GT] = PCI_EXP_LNKCTL2_TLS_128_0GT,
>  	};
>  
>  	if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
> @@ -70,7 +71,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
>  	return speed_conv[speed];
>  }
>  
> -static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
> +static inline u16 pcie_supported_speeds2target_speed(u16 supported_speeds)
>  {
>  	return __fls(supported_speeds);
>  }
> @@ -88,7 +89,7 @@ static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
>  static u16 pcie_bwctrl_select_speed(struct pci_dev *port, enum pci_bus_speed speed_req)
>  {
>  	struct pci_bus *bus = port->subordinate;
> -	u8 desired_speeds, supported_speeds;
> +	u16 desired_speeds, supported_speeds;
>  	struct pci_dev *dev;
>  
>  	desired_speeds = GENMASK(pci_bus_speed2lnkctl2(speed_req),
> diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
> index 38a41ccf79b9a..5ee8795107f26 100644
> --- a/drivers/pci/pcie/portdrv.c
> +++ b/drivers/pci/pcie/portdrv.c
> @@ -274,7 +274,7 @@ static int get_port_device_capability(struct pci_dev *dev)
>  
>  		pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap);
>  		if (linkcap & PCI_EXP_LNKCAP_LBNC &&
> -		    hweight8(dev->supported_speeds) > 1)
> +		    hweight16(dev->supported_speeds) > 1)
>  			services |= PCIE_PORT_SERVICE_BWCTRL;
>  	}
>  
> diff --git a/drivers/thermal/pcie_cooling.c b/drivers/thermal/pcie_cooling.c
> index a876d64f15827..9a2e39398674b 100644
> --- a/drivers/thermal/pcie_cooling.c
> +++ b/drivers/thermal/pcie_cooling.c
> @@ -75,6 +75,7 @@ static_assert(PCIE_SPEED_5_0GT + 1 == PCIE_SPEED_8_0GT);
>  static_assert(PCIE_SPEED_8_0GT + 1 == PCIE_SPEED_16_0GT);
>  static_assert(PCIE_SPEED_16_0GT + 1 == PCIE_SPEED_32_0GT);
>  static_assert(PCIE_SPEED_32_0GT + 1 == PCIE_SPEED_64_0GT);
> +static_assert(PCIE_SPEED_64_0GT + 1 == PCIE_SPEED_128_0GT);
>  
>  MODULE_AUTHOR("Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>");
>  MODULE_DESCRIPTION("PCIe cooling driver");

Once you start to use the new capability, you'll also need to check if the 
GENMASK()s related to speed vector are still okay (both bwctrl and core 
do it). There might also be fls() or something like that that which no 
longer holds with the 0x7 reserved hole in the speeds but I didn't check.

-- 
 i.