[PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

[PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

[Rob Herring (Arm)]

i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for
temporary buffers. The SRAM is larger than 96KB, but that is all that is
available to non-secure world.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
NXP folks, any comments on NPU freq? IIRC, the clock controller supports
setting the freq to 1GHz. Is that supported?
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 7b27012dfcb5..d826d4b5a06b 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -43,6 +43,29 @@ map0 {
 			};
 		};
 	};
+
+	sram: sram@20480000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x20480000 0x0 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x20480000 0x18000>;
+	};
+
+	soc@0 {
+		npu@4a900000 {
+			compatible = "fsl,imx93-npu", "arm,ethos-u65";
+			reg = <0x4a900000 0x1000>;
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mlmix>;
+			clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+			assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
+			assigned-clock-rates = <800000000>, <24000000>;
+		};
+	};
 };
 
 &aips1 {
-- 
2.51.0

Re: [PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

[Peng Fan]

Hi Rob,

On Thu, Feb 19, 2026 at 08:41:59AM -0600, Rob Herring (Arm) wrote:
>i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for
>temporary buffers. The SRAM is larger than 96KB, but that is all that is
>available to non-secure world.
>
>Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
>---
>NXP folks, any comments on NPU freq? IIRC, the clock controller supports
>setting the freq to 1GHz. Is that supported?

NPU supports three freqs:
500MHz for Low Drive mode
800MHz for Nominal Drive mode
1GHz for Over drive mode

The NXP downstream choose nominal drive mode for peripherals,
in NXP downstream, there is a driver to do nominal and over drive
mode switch for the SoC at runtime(through sysfs interface by user), there
is no dedicated arm core voltage supply, there is only one vdd soc supply.

To avoid introduce complexity to various drivers, drivers use nomimal freq,
so OD->ND switch does not require drivers to update its own clock frequencies.

>---
> arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
>index 7b27012dfcb5..d826d4b5a06b 100644
>--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
>+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
>@@ -43,6 +43,29 @@ map0 {
> 			};
> 		};
> 	};
>+
>+	sram: sram@20480000 {
>+		compatible = "mmio-sram";
>+		reg = <0x0 0x20480000 0x0 0x18000>;
>+		#address-cells = <1>;
>+		#size-cells = <1>;
>+		ranges = <0x0 0x0 0x20480000 0x18000>;
>+	};
>+
>+	soc@0 {
>+		npu@4a900000 {
>+			compatible = "fsl,imx93-npu", "arm,ethos-u65";
>+			reg = <0x4a900000 0x1000>;
>+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
>+			power-domains = <&mlmix>;
>+			clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
>+			clock-names = "core", "apb";
>+			sram = <&sram>;
>+			assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
>+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
>+			assigned-clock-rates = <800000000>, <24000000>;

APB could run at 133.3MHz.

Regards
Peng

>+		};
>+	};
> };
> 
> &aips1 {
>-- 
>2.51.0
>

Re: [PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

[Rob Herring]

On Tue, Feb 24, 2026 at 7:49 PM Peng Fan <peng.fan@oss.nxp.com> wrote:
>
> Hi Rob,
>
> On Thu, Feb 19, 2026 at 08:41:59AM -0600, Rob Herring (Arm) wrote:
> >i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for
> >temporary buffers. The SRAM is larger than 96KB, but that is all that is
> >available to non-secure world.
> >
> >Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> >---
> >NXP folks, any comments on NPU freq? IIRC, the clock controller supports
> >setting the freq to 1GHz. Is that supported?
>
> NPU supports three freqs:
> 500MHz for Low Drive mode
> 800MHz for Nominal Drive mode
> 1GHz for Over drive mode
>
> The NXP downstream choose nominal drive mode for peripherals,
> in NXP downstream, there is a driver to do nominal and over drive
> mode switch for the SoC at runtime(through sysfs interface by user), there
> is no dedicated arm core voltage supply, there is only one vdd soc supply.
>
> To avoid introduce complexity to various drivers, drivers use nomimal freq,
> so OD->ND switch does not require drivers to update its own clock frequencies.
>
> >---
> > arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> >diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> >index 7b27012dfcb5..d826d4b5a06b 100644
> >--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> >+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> >@@ -43,6 +43,29 @@ map0 {
> >                       };
> >               };
> >       };
> >+
> >+      sram: sram@20480000 {
> >+              compatible = "mmio-sram";
> >+              reg = <0x0 0x20480000 0x0 0x18000>;
> >+              #address-cells = <1>;
> >+              #size-cells = <1>;
> >+              ranges = <0x0 0x0 0x20480000 0x18000>;
> >+      };
> >+
> >+      soc@0 {
> >+              npu@4a900000 {
> >+                      compatible = "fsl,imx93-npu", "arm,ethos-u65";
> >+                      reg = <0x4a900000 0x1000>;
> >+                      interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> >+                      power-domains = <&mlmix>;
> >+                      clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
> >+                      clock-names = "core", "apb";
> >+                      sram = <&sram>;
> >+                      assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
> >+                      assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
> >+                      assigned-clock-rates = <800000000>, <24000000>;
>
> APB could run at 133.3MHz.

24MHz does seem a bit slow. Do you know what parent would that be?

Rob

RE: [PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

[Peng Fan (OSS)]

> Subject: Re: [PATCH] arm64: dts: freescale: imx93: Add Ethos-U65 NPU
[...]
> > >+      soc@0 {
> > >+              npu@4a900000 {
> > >+                      compatible = "fsl,imx93-npu", "arm,ethos-u65";
> > >+                      reg = <0x4a900000 0x1000>;
> > >+                      interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> > >+                      power-domains = <&mlmix>;
> > >+                      clocks = <&clk IMX93_CLK_ML>, <&clk
> IMX93_CLK_ML_APB>;
> > >+                      clock-names = "core", "apb";
> > >+                      sram = <&sram>;
> > >+                      assigned-clocks = <&clk IMX93_CLK_ML>, <&clk
> IMX93_CLK_ML_APB>;
> > >+                      assigned-clock-parents = <&clk
> IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_24M>;
> > >+                      assigned-clock-rates = <800000000>,
> > >+ <24000000>;
> >
> > APB could run at 133.3MHz.
> 
> 24MHz does seem a bit slow. Do you know what parent would that be?

Please try below:
Parent: <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
Rate: <133000000>;

Regards
Peng.

> 
> Rob