From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from MTA-13-4.privateemail.com (mta-13-4.privateemail.com [198.54.127.109]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C923A1DFD8B for ; Fri, 20 Feb 2026 17:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.54.127.109 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771607792; cv=none; b=UEav/wDwAJf0OQyLk15XVektFDAuVjPtjYS38fKJp5TTk5TTMEkcChbZhfFEjOyI4PyDrIRzoB50HjoEeCSckkVbzyZdLJnfMHY6deCX0xdeNH5DsYybVAwepXS7BzEI/QZ4krv62U7SiSthmNEn6vCrtbmeD+3KiuxT00REKGI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771607792; c=relaxed/simple; bh=Je+HbnA3LFwH1h1HGySk0tkOwJGTKrfNJdjskJtiQ/Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K4s5rHBaIHuzi0PkL+A+FpvZg7iEIgr8OPaWl+PxAzVJ79qV3sWSvo82p0mn7+NZvpgeV5KkElxLRRDyGUVdPmG0OM6lIX4a27PhMZuLBdrXZ9ttBflwypDwXDD9YJ83plmLKwaRUMyw/SQSYPvYBkh0zzM4j63PEgVTWwKTn/U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=effective-light.com; spf=pass smtp.mailfrom=effective-light.com; arc=none smtp.client-ip=198.54.127.109 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=effective-light.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=effective-light.com Received: from mta-13.privateemail.com (localhost [127.0.0.1]) by mta-13.privateemail.com (Postfix) with ESMTP id 4fHcNb0JH6z3hhTQ; Fri, 20 Feb 2026 12:16:31 -0500 (EST) Received: from localhost.localdomain (bras-base-toroon4332w-grc-26-174-91-51-28.dsl.bell.ca [174.91.51.28]) by mta-13.privateemail.com (Postfix) with ESMTPA; Fri, 20 Feb 2026 12:16:03 -0500 (EST) From: Hamza Mahfooz To: dri-devel@lists.freedesktop.org Cc: =?UTF-8?q?Michel=20D=C3=A4nzer?= , Mario Limonciello , Hamza Mahfooz , Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Alex Hung , Aurabindo Pillai , Wayne Lin , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Ivan Lipski , Dominik Kaszewski , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/2] drm/amd/display: add vendor specific reset Date: Fri, 20 Feb 2026 12:15:13 -0500 Message-ID: <20260220171518.711594-2-someguy@effective-light.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260220171518.711594-1-someguy@effective-light.com> References: <20260220171518.711594-1-someguy@effective-light.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Virus-Scanned: ClamAV using ClamSMTP We now have a means to respond to page flip timeouts. So, hook up support by trying to reload DMUB firmware if drm_atomic_helper_wait_for_flip_done() fails. Also, send out a wedged event if the firmware reload fails. Signed-off-by: Hamza Mahfooz --- v2: send a wedged event instead of attempting a GPU reset. v3: read return value of drm_atomic_helper_wait_for_flip_done(). v4: only send wedged event if firmware reload fails and send out "fake" page flip completes. --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7c51d8d7e73c..0ae6ada22fb0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -87,6 +87,7 @@ #include #include #include +#include #include #include #include @@ -10829,6 +10830,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; int crtc_disable_count = 0; + struct amdgpu_crtc *acrtc; trace_amdgpu_dm_atomic_commit_tail_begin(state); @@ -11085,8 +11087,26 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Signal HW programming completion */ drm_atomic_helper_commit_hw_done(state); - if (wait_for_vblank) - drm_atomic_helper_wait_for_flip_done(dev, state); + if (wait_for_vblank && + drm_atomic_helper_wait_for_flip_done(dev, state)) { + mutex_lock(&dm->dc_lock); + if (dm_dmub_hw_init(adev)) + drm_dev_wedged_event(dev, DRM_WEDGE_RECOVERY_REBIND | + DRM_WEDGE_RECOVERY_BUS_RESET, + NULL); + mutex_unlock(&dm->dc_lock); + + spin_lock_irqsave(&dev->event_lock, flags); + drm_for_each_crtc(crtc, dev) { + if (acrtc->event) { + drm_crtc_send_vblank_event(crtc, acrtc->event); + acrtc->event = NULL; + drm_crtc_vblank_put(crtc); + acrtc->pflip_status = AMDGPU_FLIP_NONE; + } + } + spin_unlock_irqrestore(&dev->event_lock, flags); + } drm_atomic_helper_cleanup_planes(dev, state); -- 2.53.0