From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3F333783C5 for ; Mon, 23 Feb 2026 21:55:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771883743; cv=none; b=o3bqsCe2+IjXW93xz34YCZzqWY7pXAPIL2cd2mWbLBlswjT5+knVzda4Wj/EIPUlGxrpzrUoEpDvQ3BYU5wt73jxSrrSmdUYGmf8reCCKk2C8InvgLex3XIJztv2cQlabTMDsgcAHzrbhJ9AXQpPHFDGR3a6wX1Q0I5SUXQL5LI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771883743; c=relaxed/simple; bh=s9r6LQpkXjN+XXU2081UOBJ436iMLnCbqyDWradBeCs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Qx8Taud5v1dET6OVNJpjTlqbbmYSmwZx0a+SbA+dxmta5Dj3ZTp1bTq2VrXCR93+byM2xHTKG2/kKMwDeFq/tmOU+ovQ7J3qtX47qAlu6DqRM8qrHpe9qOsvb8v07uxx6njOuT+mBGjHjXSyNIJGhNzwJrGqHULsuKt6jKHuZmw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=h2lr1ral; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="h2lr1ral" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=Wal6zQUDwWjl4G1zkfqeCq1MvEwfhT1p43+e3oyXIpc=; b=h2lr1raluw6LE1c2cK1uMHUvmm +28SSRdFEZxClWNG2Upkjete2it5h+alAeK9mvzCFeOf9oZewhb8JUil0W/4K0O5DLZQMYDYBRY7J UhKxGK7lxeUQEiIE6I7DSHRJ75156Ah7MkwWgFVzIk6kCV8SFexXTLx5RMiASKNQoLjEhT+SjpAfi zMqKTw1OJLytGCcZqOwFutKK41O8dJ1f3H/PscRO9xD1kIaMY2q4AldC9s10iCc+OUu/Q7U9t00fu bvVOEpKAxoUo1VKbLOm7r4+OpCI852c+zqvgdJWlHHdfGNK4FHbHmpB9jajz5n/JYVRhTm6aSR22+ 38K5U/nw==; Received: from 2001-1c00-8d85-5700-266e-96ff-fe07-7dcc.cable.dynamic.v6.ziggo.nl ([2001:1c00:8d85:5700:266e:96ff:fe07:7dcc] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1vudtB-00000005zZ0-0Udr; Mon, 23 Feb 2026 21:54:52 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 6DF6C30330E; Mon, 23 Feb 2026 22:54:36 +0100 (CET) Date: Mon, 23 Feb 2026 22:54:36 +0100 From: Peter Zijlstra To: Mathieu Desnoyers Cc: David Laight , linux-kernel@vger.kernel.org, Thomas Gleixner , Mark Rutland , cmarinas@kernel.org, maddy@linux.ibm.com, hca@linux.ibm.com, ryan.roberts@arm.com Subject: Re: [RFC] in-kernel rseq Message-ID: <20260223215436.GS1282955@noisy.programming.kicks-ass.net> References: <20260223163843.GR1282955@noisy.programming.kicks-ass.net> <20260223175357.481c161e@pumpkin> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Feb 23, 2026 at 01:22:18PM -0500, Mathieu Desnoyers wrote: > > I think it would be better as the address of the instruction after > > the 'store'. > > That's indeed what we do for userspace rseq. Either works I suppose. The only think to be careful about is that you must not restart once the store has happened. > > You probably don't need separate 'begin' and 'restart' addresses. > > It's not needed as long as the abort behavior is only restart. It > becomes useful if another behavior is wanted on abort. But since > this is kernel code and not ABI, it can change if the need arise. Right, didn't want to limit to restart, although that is what is used here. > > It might be enough to save the 'restart' address and a byte length > > directly in 'current', much simpler code. > > That would make it two stores to the task struct. Those would not be > single-instruction, so we'd have to deal with preemption coming between > those two stores. Also this would be more code: two stores compared > to a single pointer store to the task struct to begin the critical > section. AFAIU Peter's proposed approach is more efficient. Must indeed be a single store. Either we have it set in full, or we don't. > We could turn the end address into a length if we want, this would > make it more alike the userspace rseq ABI counterpart. I find 3 distinct addresses easier to fill out, but again it doesn't matter. > > How much it helps is another matter. > > I'm sure I remember something about per-cpu data being used for something > > because it was faster then using 'current' - not sure of the context. > > The problem with per-cpu data for this is how to handle migration ? > The whole point of this is to replace preempt disable. This; it cannot be a per-cpu address, if you need it to implement per-cpu ops. > > The real problem with rseq is they don't scale. > > Not sure what you mean. They don't scale with respect to what ? He might be talking about forward progress instead of scaling. There are indeed foward progress concerns with rseq -- as there are with trivial LL/SC. But given the length of a slice vs the length of a rseq section, this should be a non-issue. Doing the restart on interrupt would be a bigger issue. Although even there I think that since the operations we're talking about are but a few instructions, it should all just work well enough. And if not, you can always craft a restart path that does the actual local_irq_disable(). Eg. this_cpu_add(pcp, i) { static const struct sched_seq _R = { .begin = &&__rseq_begin, .commit = &&__rseq_commit, .restart = &&__rseq_restart, }; WRITE_ONCE(current->sched_rseq, &_R); __rseq_begin: barrier(); addr = raw_cpu_ptr(pcp); v = READ_ONCE(*addr) v += i; WRITE_ONCE(*addr, v); barrier(); __rseq_commit: WRITE_ONCE(current->sched_rseq, NULL); return; __rseq_restart: guard(irqsave)(); addr = raw_cpu_ptr(pcp); v = READ_ONCE(*addr) v += i; WRITE_ONCE(*addr, v); return; } That way you get fast most of the time, except when you did do get an interrupt in between. > > I think that is just unlocked RMW of a per-cpu/thread variable. That's missing the point entirely. He might be stuck in x86_64 or something.