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Tue, 24 Feb 2026 04:20:36 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 3/5] PCI: tegra: Simplify clock handling by using clk_bulk*() functions Date: Tue, 24 Feb 2026 17:48:59 +0530 Message-ID: <20260224121948.25218-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently, the driver acquires clocks and prepare/enable/disable/unprepare the clocks individually thereby making the driver complex to read. The driver can be simplified by using the clk_bulk*() APIs. Use: - devm_clk_bulk_get_all() API to acquire all the clocks - clk_bulk_prepare_enable() to prepare/enable clocks - clk_bulk_disable_unprepare() APIs to disable/unprepare them in bulk As part of this cleanup: - Remove the legacy has_cml_clk flag - Drop explicit handling of individual clocks (pex, afi, pll_e, cml) - Rely on device tree ordering for clock sequencing, eliminating hardcoded logic and improving readability and maintainability This improves clarity, and makes future changes easier for maintainers. Cc: Thierry Reding Signed-off-by: Anand Moon --- v3: None v2: Switch back to devm_clk_bulk_get_all from devm_clk_bulk_get() Mani - But you are converting it to .yaml, so you can safely use devm_clk_bulk_get_all() v1: Switch from devm_clk_bulk_get_all() -> devm_clk_bulk_get() with fix clks array. nvidia,tegra20-pcie and nvidia,tegra186-pcie uses three clocks pex, afi, pll_e where as nvidia,tegra30-pcie, nvidia,tegra124-pcie, nvidia,tegra210-pcie uses four clks pex, afi, pll_e, cml --- drivers/pci/controller/pci-tegra.c | 71 +++++------------------------- 1 file changed, 12 insertions(+), 59 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 512309763d1f..32dc11d95cc9 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -298,7 +298,6 @@ struct tegra_pcie_soc { bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; - bool has_cml_clk; bool has_gen2; bool force_pca_enable; bool program_uphy; @@ -331,10 +330,8 @@ struct tegra_pcie { struct resource cs; - struct clk *pex_clk; - struct clk *afi_clk; - struct clk *pll_e; - struct clk *cml_clk; + struct clk_bulk_data *clks; + int num_clks; struct reset_control *pex_rst; struct reset_control *afi_rst; @@ -1154,15 +1151,11 @@ static void tegra_pcie_enable_controller(struct tegra_pcie *pcie) static void tegra_pcie_power_off(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; - const struct tegra_pcie_soc *soc = pcie->soc; int err; reset_control_assert(pcie->afi_rst); - clk_disable_unprepare(pcie->pll_e); - if (soc->has_cml_clk) - clk_disable_unprepare(pcie->cml_clk); - clk_disable_unprepare(pcie->afi_clk); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1175,7 +1168,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie) static int tegra_pcie_power_on(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; - const struct tegra_pcie_soc *soc = pcie->soc; int err; reset_control_assert(pcie->pcie_xrst); @@ -1203,35 +1195,16 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) } } - err = clk_prepare_enable(pcie->afi_clk); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err < 0) { - dev_err(dev, "failed to enable AFI clock: %d\n", err); + dev_err(dev, "filed to enable clocks: %d\n", err); goto powergate; } - if (soc->has_cml_clk) { - err = clk_prepare_enable(pcie->cml_clk); - if (err < 0) { - dev_err(dev, "failed to enable CML clock: %d\n", err); - goto disable_afi_clk; - } - } - - err = clk_prepare_enable(pcie->pll_e); - if (err < 0) { - dev_err(dev, "failed to enable PLLE clock: %d\n", err); - goto disable_cml_clk; - } - reset_control_deassert(pcie->afi_rst); return 0; -disable_cml_clk: - if (soc->has_cml_clk) - clk_disable_unprepare(pcie->cml_clk); -disable_afi_clk: - clk_disable_unprepare(pcie->afi_clk); powergate: if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1255,25 +1228,11 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; - const struct tegra_pcie_soc *soc = pcie->soc; - - pcie->pex_clk = devm_clk_get(dev, "pex"); - if (IS_ERR(pcie->pex_clk)) - return PTR_ERR(pcie->pex_clk); - pcie->afi_clk = devm_clk_get(dev, "afi"); - if (IS_ERR(pcie->afi_clk)) - return PTR_ERR(pcie->afi_clk); - - pcie->pll_e = devm_clk_get(dev, "pll_e"); - if (IS_ERR(pcie->pll_e)) - return PTR_ERR(pcie->pll_e); - - if (soc->has_cml_clk) { - pcie->cml_clk = devm_clk_get(dev, "cml"); - if (IS_ERR(pcie->cml_clk)) - return PTR_ERR(pcie->cml_clk); - } + pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); + if (pcie->num_clks < 0) + return dev_err_probe(dev, pcie->num_clks, + "failed to get clocks\n"); return 0; } @@ -2344,7 +2303,6 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_pex_clkreq_en = false, .has_pex_bias_ctrl = false, .has_intr_prsnt_sense = false, - .has_cml_clk = false, .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, @@ -2373,7 +2331,6 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, - .has_cml_clk = true, .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, @@ -2394,7 +2351,6 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, - .has_cml_clk = true, .has_gen2 = true, .force_pca_enable = false, .program_uphy = true, @@ -2417,7 +2373,6 @@ static const struct tegra_pcie_soc tegra210_pcie = { .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, - .has_cml_clk = true, .has_gen2 = true, .force_pca_enable = true, .program_uphy = true, @@ -2458,7 +2413,6 @@ static const struct tegra_pcie_soc tegra186_pcie = { .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, - .has_cml_clk = false, .has_gen2 = true, .force_pca_enable = false, .program_uphy = false, @@ -2642,7 +2596,7 @@ static int tegra_pcie_pm_suspend(struct device *dev) } reset_control_assert(pcie->pex_rst); - clk_disable_unprepare(pcie->pex_clk); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); @@ -2676,9 +2630,9 @@ static int tegra_pcie_pm_resume(struct device *dev) if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_enable_msi(pcie); - err = clk_prepare_enable(pcie->pex_clk); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { - dev_err(dev, "failed to enable PEX clock: %d\n", err); + dev_err(dev, "failed to enable clock: %d\n", err); goto pex_dpd_enable; } @@ -2699,7 +2653,6 @@ static int tegra_pcie_pm_resume(struct device *dev) disable_pex_clk: reset_control_assert(pcie->pex_rst); - clk_disable_unprepare(pcie->pex_clk); pex_dpd_enable: pinctrl_pm_select_idle_state(dev); poweroff: -- 2.50.1