From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EBE61F09B3; Tue, 24 Feb 2026 23:54:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771977274; cv=none; b=WI1cVV4j7Ue0fUg8CcDUsKQ9lbESMDohEHHbLaLzRQddEZRaf8vvDXrhbEPPom5uOlqxwSjk/Qy2B5G024/3pz+9frCG1xle45agPQIwuTNTRwvMfnB3n4+UL0eMgqVTOW0LFjZFscfDYdBPmOETFHZf4viWxBqL4Ypp1B8DoIQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771977274; c=relaxed/simple; bh=qexNreA3noaNpoPwWdD70RuBwyt5EeVZfegYyF8m7cc=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=krmPNeJD1azk0Fdxqf4AjMCZYmE2ZkV2yoU/ZwD8Bt7nSdEqFt64qp1vdPDd+QAI6/eWOKK2XXSYt6mHzQ/mqhtBVH8SCpmsQhzaIZSb5yRdE/sbcY8OxkmtmT06G/+UxwLV7LxH83Xw/CmfCQvSuzJoesSQB5KjdECKhoCj8VM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oYEB647E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oYEB647E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F04A3C116D0; Tue, 24 Feb 2026 23:54:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771977273; bh=qexNreA3noaNpoPwWdD70RuBwyt5EeVZfegYyF8m7cc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=oYEB647EzJmppp/2RB2bNjz4U0zSLzPjLUfECABrKnqfFxl+OI7hqQFEcBtVo9iGy Idk9r8iZ+MvGV0MybLailS6CIxs+/gpyO0kpcx3H10OyQLE+xCA8YRRMCBXQaShI3D l1cTz7x1yqwpoiFcS0MOLS1s56hTRM5u5hUYf4wxv733xFiJJayQ9Rt72FeuUxpaD8 EvAO92aDeQmyq/dRGZfDsT0CCqH/nYSmuwGj8ZcR8eG1uP235JgGTURChoN+K52SxF ATa7KpKdkHeN4IVT23VYAh9l1qkyeqQjwrwkeDEhFUuDtraPFBwIuZ/ye62yniLf3v /dPrkRzEjGJhw== Date: Tue, 24 Feb 2026 15:54:32 -0800 From: Jakub Kicinski To: Siddharth Vadapalli Cc: , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH net 1/3] net: ethernet: ti: am65-cpsw-nuss: set irq_disabled after disabling RX IRQ Message-ID: <20260224155432.15ded392@kernel.org> In-Reply-To: References: <20260220041431.372610-1-s-vadapalli@ti.com> <20260220041431.372610-2-s-vadapalli@ti.com> <20260223184803.739c17a7@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 24 Feb 2026 10:40:05 +0530 Siddharth Vadapalli wrote: > CPU1 sees irq_disabled being 'true' and before it updates it to 'false', if > CPU2 also sees irq_disabled > being 'true', both CPU1 and CPU2 will enter the IF-condition and eventually > invoke enable_irq(). I think the races are just between NAPI and the HARD IRQ context. There can only be one NAPI scheduled for a queue, I assume. > Please let me know if this is what you were referring to. I will use atomic > APIs at all places to update > 'irq_disabled'. I recommend a spin lock, unless you can measure as significant difference. Locks and atomics have similar cost on many CPUs. And juggling local state, IRQ state, and NAPI state atomically will get tricky.